Introduction to ASIC,FPGA,PLDs (16 marks)

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Presentation transcript:

Introduction to ASIC,FPGA,PLDs (16 marks) CH.6 Introduction to ASIC,FPGA,PLDs (16 marks) Visit for more Learning Resources

XC 9500 CPLD Family Features- 1.High performance 2. Large density range. 3. Flexible 36 Vs 18 functional blocks. 4. Slew rate control on each individual output. 5. User programmable ground pin capability. 6.High drive 24 mA outputs. Advanced CMOS 5V fast FLASH technology.

Continued… XC 9536- 36 macro cells- 2F.B. XC 9500 CPLD family provides advanced in- system programming and test capabilities for high performance, general purpose integration.

CPLD XC9500 Architecture

Functional Block Programmable gate array Product term Allocator Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 Macrocell 9 Macrocell 10 Macrocell 11 Macrocell 12 Macrocell 13 Macrocell 14 Macrocell 15 Macrocell 16 Macrocell 17 Macrocell 18 To fast connect switch 18 out From fast connect switch 18 18 out

Product Term allocator

Macrocell

Input output block

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