ENG6530 Reconfigurable Computing Systems General Information Handout Winter 2017, January 10th

Shawki Areibi Office, Email, Phone Research Interests Office: 2335, EXT 53819 Email: sareibi@uoguelph.ca Web: http://www.uoguelph.ca/~sareibi Office Hour: Thursday 2:00 – 3:00 PhD, Waterloo 1995 Research Interests VLSI Physical Design Automation (CAD/EDA) Combinatorial Optimization (Heuristics/Meta-heuristics) Reconfigurable Computing Systems/Embedded Systems RCS - Winter 20174

Outline Staff (TA, Lab Tech) Lecture Schedule Course Text and References Resources and Communication Assignments, Paper Review, Project Evaluation Course contents, Tentative Schedule RCS - Winter 20174

Lab Coordinator Kyle Montgomery Thornbrough Building Room 2308, ext 53873 Email: kmontgomery@uoguelph.ca RCS - Winter 20174

Lecture Schedule Lectures 15:00 – 16:20 (Tue/Thur) In RICH 2531 RCS - Winter 20174

Text Book and References Text Books & References “Reconfigurable Computing: The Theory and Practice of FPGA-Based Computing”, Edited by S. Hauck, 2008. “Introduction to Reconfigurable Computing: Architectures, Algorithms and Applications”, by C.Bobda “Reconfigurable Computing: Accelerating Computation with FPGAs”, by Maya Gokhale “Computer Organization and Design”, by Patterson and Hennessy “VHDL for Engineers”, by K. Short, 2009. “The Designer’s Guide to VHDL”, by Peter Ashenden RCS - Winter 20174

Resources & Communication http://www.uoguelph.ca/~sareibi Communications E-mail ENG6530/ENG3050 Web Pages Username: Password: User Name:engg6530 Pw: rcs2014 RCS - Winter 20174

Prerequisites Digital Design (ENG2410) Computer Organization (ENG3380) Basic knowledge of programming languages (C, C++) Basic Knowledge of Hardware Description Languages (VHDL) Experience in VLSI Design maybe helpful but not required. RCS - Winter 20174

Course Objectives Achieves the following goals: Gives an overview of the traditional Von Neumann Computer Architecture, its specifications, design and implementations and main drawbacks. Techniques to improve the performance. Teaches you the internal structure of Programmable Logic in general and Field Programmable Gate Arrays in particular. Teaches you how digital circuits are designed today using advanced CAD tools and HDLs and high level languages. Teaches you the basic concepts of Reconfigurable Computing systems (Hardware/Software co-design) Teaches you when/how to apply Reconfigurable Computing Concepts to design efficient, reliable, robust systems (DSP). Understand the concept of Run Time Reconfiguration. RCS - Winter 20174

Evaluation Topic Weight Details Assignments 20% Paper Review 10% See Web Page Project 30% Final Exam 40% Closed Book Exam RCS - Winter 20174

Paper Review Each student (group) is assigned several articles from journal papers/conferences. Prepare a brief (20 minute) oral presentation of the article or topic (objectives, methods, results, contributions e.t.c.) A Two page summary giving the citation and the material in the oral presentation must be written and a copy is distributed to each class member. RCS - Winter 20174

Paper Review: Topics Coarse Grained Reconfigurable Arrays Evolvable Hardware Floating Point vs. Fixed Point representations CAD for RCS (High Level Synthesis) Operating Systems for Reconfigurable Computing Electronic System Level: A comparison ASICs vs. FPGAs vs. ASIPs Run Time Reconfiguration: Challenges Others … RCS - Winter 20174

Research Project “Graduate Students” will select a topic related to Reconfigurable Computing Systems. You should conduct an in-depth study covering the problem to be solved and its current status. Your finding should be documented in a report Introduction to the problem Motivation Background Literature Review Methodology Results Conclusion RCS - Winter 20174

What is Reconfigurable Computing? Mapping algorithms traditionally running on general purpose processors onto reconfigurable platforms to achieve better performance. Computation using hardware that can adapt at the logic level to solve specific problems Why is this interesting/important? Some applications are poorly suited to General microprocessors. VLSI “explosion” provides increasing resources. Hardware/Software Co-design is main trend in Embedded Systems. Accelerate scientific/industrial applications to achieve speedup (Real Time performance is necessary!) RCS - Winter 20174

Microprocessor-based Systems Von-Neumann Architecture Data Storage (Register File) A B C ALU 64 Characteristics? Generalized to perform many functions well. Operates on fixed data sizes. Instruction fetch, decode, execute  Inherently sequential. RCS - Winter 20174

Reconfigurable Computing If (A > B) { H = A; L = B; } Else { H = B; L = A; Functional Unit H L Create specialized hardware for each application. Functional units optimized to perform a special task. RCS - Winter 20174

Implementation Spectrum Microprocessor Reconfigurable Hardware ASIC Characteristics? ASIC gives high performance but is inflexible and expensive Processor is very flexible but not tuned to the application. Reconfigurable hardware is a nice compromise. RCS - Winter 20174

Tentative Schedule Topic #1, Introduction to RCS Topic #2, Programmable Logic Devices Topic #3, CAD for RCS (FPGAs) Topic #4, VHDL Topic #5, High Level Languages (Handel-C) Topic #6, Reconfigurable Processors (ASIPs) Topic #7, Hardware/Software Co-design Topic #8, Run Time Reconfigurations Topic #9, Digital Signal Processing, Tools Topic #10, Design Exploration Techniques Topic #11, RCS Applications RCS - Winter 20174

Topic #1: RCS, Introduction Identify bottlenecks currently found in traditional Von Neumann Architectures. Learn new techniques to improve performance. How/Why RCS can fill the gap between ASICs and General Purpose Processors. RCS - Winter 20174

Topic #1, Cont ..: Technology Comparison Performance Cost Power Flexibility Memory BW I/O BW GPP PDSP ASIC FPGA LOW Med-High HIGH Medium LOWt Low-Medium RCS - Winter 20174

Topic #2: Programmable Logic Or Array Programmable AND array Programmable AND array Programmable Or Array RCS - Winter 20174

Topic #2 Cont … : FPGAs Around the beginning of the 1980s, it became apparent that there was a gap in the digital IC continuum. At one end, there were programmable devices liks SPLDs and CPLDs, which were highly configurable but could not support large designs. At the other end of the spectrum were ASICs which can support complex functions but were expensive, time consuming, …. RCS - Winter 20174

Topic #3: CAD for Programmable Logic Design Entry Synthesis Logic Optimization Placement Packing LUTs to CLBs Mapping to k-LUT Routing Simulation Configure an FPGA RCS - Winter 20174

Topic #3: FPGA Design Flow Design Specification Design Entry/RTL Coding Behavioral or Structural Description of Design RTL Simulation Functional Simulation Verify Logic Model & Data Flow (No Timing Delays) LE MEM I/O Synthesis Translate Design into Device Specific Primitives Optimization to Meet Required Area & Performance Constraints Place & Route Map Primitives to Specific Locations inside Target Technology with Reference to Area & Performance Constraints Specify Routing Resources to Be Used RCS - Winter 20174

Topic #4: VHDL External Interface circuit Internal Functionality B Outputs Inputs RCS - Winter 20174

Topic #4: Synthesizable VHDL VHDL for Simulation VHDL for Synthesis VHDL for Specification VHDL for Synthesis of Arithmetic Circuits RCS - Winter 20174

Topic #5: Managing Complexity ESL RCS - Winter 20174

Topic #5: High Level Languages Take an algorithm written in C. Generate an efficient hardware design, run it on an FPGA. Fast design cycle, easy to maintain code. C programmers should be able to create fast hardware! RCS - Winter 20174

Topic #6: ASIPs An ASIP is a stored-memory CPU whose architecture is tailored for a particular set of applications. The instruction-sets tailored to specific applications or application domains RCS - Winter 20174

Topic #7: Hardware/Software Co-design Interface process (a, b, c) in port a, b; out port c; { read(a); … write(c); } Specification Line () { a = … … detach } Partition FPGA Model Capture Synthesize Processor RCS - Winter 20174

Topic #8: RTR FPGAs are classified as dynamically reconfigurable if their embedded configuration storage circuitry and corresponding functions can be updated without disturbing the operation of the remaining logic. RCS - Winter 20174

Topic #8, Cont ..: Virtual Hardware The concept of Run Time Reconfiguration on FPGAs is similar to the concept of Virtual Memory on Computer Systems. RCS - Winter 20174

Topic#9: DSP RCS - Winter 20174

Topic #9: DSP, Performance Gap Algorithmic complexity increases as application demands increase. In order to process these new algorithms, higher performance signal processing engines are required RCS - Winter 20174

Topic #10: Design Exploration Given an application (software implementation): what is the most appropriate hardware components and communication links that should be used? The main challenge in DSE arises from the sheer size of the design space that must be explored. Typically, a large system has millions, if not billions, of possibilities, and so enumerating every point in the design space is prohibitive. RCS - Winter 20174

Topic #11: Applications What applications require Hardware Acceleration? Image processing, medical applications, real time … Hardware Accelerators for CAD Hardware Accelerators for ANNs Hardware Accelerators for Communication Systems RCS - Winter 20174

Satellite Imaging GMTI processing chain RCS - Winter 20174 Satellite imaging used for mapping, environmental studies and defense applications High-data rate and low-power demands of space require cutting-edge technology such as RC to provide required processing capabilities Including RC devices in the processing chain will eventually enhance performance c/o US Air Force c/o LANL c/o LANL GMTI processing chain RCS - Winter 20174

fMRI and Real-time Human Body Imaging Technique for determining which parts of the brain are activated by different types of physical sensation or activity – “brain mapping” High- and low-resolution scans compared using numerous FFTs Typically post-processed Much error correction needed due to subject movement 3D data representation requires a good deal of conventional processing Studying how RC devices can achieve real-time processing Figures c/o University of Oxford, UK RCS - Winter 20174

Questions? RCS - Winter 20174