CHaRy Software Synthesis for Hard Real-Time Systems Peter Altenbernd C-LAB (= Siemens IC & Uni Paderborn) Paderborn, GERMANY peter@c-lab.de http://www.c-lab.de/~peter/CHaRy
Outline Real-Time Systems CHaRy - Software Synthesis SEA & Software Circuits CHaRy++ = CHaRy + Statecharts
Real-Time Systems ? Real-Time = Fast RT = PREDICTABLE SOFT STATIC DYNAMIC HARD 6
Why? Do You fly on Jets? “Advanced jet engines can BLOW up if Motivation Why? Do You fly on Jets? “Advanced jet engines can BLOW up if correct control inputs are not applied every 20-50 ms” 5
Claim!! Many RTS cannot be designed with traditional (non-RT) methods We need to provide a priori guarantees “provable correct designs” 4
Saving Cost by Real-Time Designs "Using NRTA's Volcano CAN controller software, based on fundamental real-time research results, Volvo safes 10$ per car, because cheaper devices are sufficient." K.Tindell, NRTA, during his presentation at the "Automotive Seminar" in Göteborg, April 23, 1998
Automation of Controller Design High-Level Frontend (e.g. SEA)
CHaRy's Benefits Software Synthesis: The application is described on a high level, whereas the implementation is left to CHaRy Suitable for both parallel and distributed systems Proper real-time handling throughout the system The user can focus on the actual problem: the application The user can try different HW architectures (network, processors) Front-end, back-end, HW to be used, and objective function are customisable
CHaRy: The C-LAB Hard Real-Time System Problem decomposition: Use of efficient heuristics for each sub-problem
Partitioning Abstract: Decomposing a program into a number of independent but communicating tasks Motivation: Finding a reasonable trade-off between task granularity and communication overhead Based on average computation time of statements and average communication cost Simple heuristic to minimize the average response time of each controller (including OS overhead)
Code Generation & Partitioning
Timing Analysis Abstract: Estimating worst-case execution time, WCET of each task Motivation: Is needed to guarantee deadlines If underestimated: serious failures If overestimated: waste of resources Independend from input data, without user annotations Low-level: caching & pipelining analysis High-level: Longest Executable Path Search (LEPS)
Timing Analysis of Straight-Line Code Efficient sequence: Caching Analysis - Pipelining Analysis - LEPS Caching Analysis: Unique handling of both data and instruction caches Relatively HW-independent (caches are easy to describe) Pipeline-independent Pipelining Analysis: Abstract description of each Basic Block is used concatenate BBs to paths Quite HW-dependent
Allocation Abstract: Static allocation algorithm for periodic hard real-time tasks Motivation: Allocation problem is NP-hard Separated allocation & scheduling Definable objective function (including both event-driven and time-triggered parts) Combination of "Slack Method" and Simulated Annealing
Schedulability Analysis Abstract: Checking whether hard real-time conditions are met Motivation: Needed during simulated annealing to analyse scheduling (e.g. DMS) Accurately computing all maximum response times (i.e longest time from period begin to completion) to check them against the corresponding deadlines Can include both event-driven and time-triggered tasks
Timing Analysis, Scheduling & Allocation Task Graph: Task Assignments:
SEA Environment Offline Simulation and Animation Modeling of Heterogenous Systems Predicate/Transition Nets Abstract Graphical Representation for Interfaces User Defined Graphical Libraries (Components) User Defined Interactions (Panels) Interactive Animation 1
SEA & Software Circuits 1
CHaRy++ = CHaRy + Statecharts 1
Conclusion SW synthesis for hard real-time systems CHaRy: customisable architecture SEA: customisable front-end CHaRY++: context of sychronous languages Real-time research results: HW-level timing analysis SW-level timing analysis allocation & schedulability testing analysis of sychronous languages Consulting for code generation problems