Chapter 2: Computer Function And Interconnection Chapter Two : Computer Function And Interconnection Chapter 2: Computer Function And Interconnection

Program Concept Hardwired systems are inflexible Chapter Two : Computer Function And Interconnection Program Concept Hardwired systems are inflexible General purpose hardware can do different tasks, given correct control signals Instead of re-wiring, supply a new set of control signals

What is a program? A sequence of steps Chapter Two : Computer Function And Interconnection What is a program? A sequence of steps For each step, an arithmetic or logical operation is done For each operation, a different set of control signals is needed The basic function of computer – execute a program (a set of instructions stored in memory)

Function of Control Unit Chapter Two : Computer Function And Interconnection Function of Control Unit For each operation a unique code is provided e.g. ADD, MOVE A hardware segment accepts the code and issues the control signals We have a computer!

Chapter Two : Computer Function And Interconnection Components The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit Data and instructions need to get into the system and results out Input/output Temporary storage of code and results is needed Main memory

Computer Components: Top Level View Chapter Two : Computer Function And Interconnection Computer Components: Top Level View

Chapter Two : Computer Function And Interconnection Instruction Cycle The CPU’s activity at any instant is instruction processing, except when the CPU is in HALT state. Two steps: Fetch (processor reads instructions from memory) Execute

Chapter Two : Computer Function And Interconnection Fetch Cycle Program Counter (PC) holds address of next instruction to fetch Processor fetches instruction from memory location pointed to by PC Increment PC Unless told otherwise Instruction loaded into Instruction Register (IR) Processor interprets instruction and performs required actions

Execute Cycle Processor-memory Chapter Two : Computer Function And Interconnection Execute Cycle Processor-memory data transfer between CPU and main memory Processor-I/O Data transfer between CPU and I/O module Data processing Some arithmetic or logical operation on data Control Alteration of sequence of operations e.g. jump Combination of above

Example of Program Execution (ADD B,A) Chapter Two : Computer Function And Interconnection Example of Program Execution (ADD B,A) 3 instruction cycles Each consisting of fetch cycle and execute cycle. Fetch the ADD instruction Read the content of memory location A into the processor Read the content of memory location B into the processor Add the two values Write the result from the processor to memory location A

Instruction Cycle State Diagram Chapter Two : Computer Function And Interconnection Instruction Cycle State Diagram

Chapter Two : Computer Function And Interconnection Interrupt concept Interrupt is a signal or an event used to request the CPU to suspend the current program execution. Occurs when an event inside a computer system requiring some urgent action by the CPU. CPU suspends the current program execution and branches in to an Interrupt Service Routine (ISR). ISR is a program that service the interrupt by taking appropriate actions. Before taking up ISR, CPU stores the next instruction address (contents of Program Counter) at the time of branching to ISR After execution of ISR, the CPU returns back to the interrupted program. The CPU resumes the interrupted program.

Chapter Two : Computer Function And Interconnection Interrupt concept Interrupts are provided as a way to improve processing efficiency. Most external devices are much slower than the processor. E.g. : processor transferring data to a printer using the instruction cycles. After each write operation, the processor must pause and remain idle ---> wasteful use of the processor. With interrupts, the processor can be engaged in executing other instructions while an i/o operation is in progress.

Chapter Two : Computer Function And Interconnection Program Flow Control

Program Timing: Short I/O Wait Chapter Two : Computer Function And Interconnection Program Timing: Short I/O Wait

Program Timing: Long I/O Wait Long Wait

Chapter Two : Computer Function And Interconnection Interrupts Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing Classes of interrupts Program e.g. overflow, division by zero Timer Generated by internal processor timer Used in pre-emptive multi-tasking I/O Generated by I/O controller Hardware failure e.g. power failure, memory parity error

Instruction Cycle with Interrupts Chapter Two : Computer Function And Interconnection Instruction Cycle with Interrupts

Interrupt Cycle Added to instruction cycle Chapter Two : Computer Function And Interconnection Interrupt Cycle Added to instruction cycle Processor checks for interrupt Indicated by an interrupt signal If no interrupt, fetch next instruction If interrupt pending: Suspend execution of current program Save context (save the current PC) Set PC to start address of interrupt handler routine Process interrupt Restore context (stored PC) and continue interrupted program

Transfer of Control via Interrupts Chapter Two : Computer Function And Interconnection Transfer of Control via Interrupts (Current Program) Branch Interrupt occurs here After commencement of the i-th instruction. ISR Return

Instruction Cycle (with Interrupts) - State Diagram Chapter Two : Computer Function And Interconnection Instruction Cycle (with Interrupts) - State Diagram

Multiple Interrupts Not only single but multiple interrupts at a time. Chapter Two : Computer Function And Interconnection Multiple Interrupts Not only single but multiple interrupts at a time. E.g: A program receiving data from communications line and printing results 2 Approaches to deal with multiple interrupts:- Disable interrupts Processor will ignore further interrupts whilst processing one interrupt Interrupts remain pending and are checked after first interrupt has been processed Interrupts handled in sequence as they occur Define priorities Low priority interrupts can be interrupted by higher priority interrupts When higher priority interrupt has been processed, processor returns to previous interrupt

Sequential Interrupt processing Chapter Two : Computer Function And Interconnection Sequential Interrupt processing

Multiple Interrupts – Nested Chapter Two : Computer Function And Interconnection Multiple Interrupts – Nested

Time Sequence of Multiple Interrupts Chapter Two : Computer Function And Interconnection Time Sequence of Multiple Interrupts Priority : Printer (2),disk(4),communication(5)

Interconnection Structures Chapter Two : Computer Function And Interconnection Interconnection Structures A computer consists of a set of components or modules of three basic types (processor, memory, I/O) that communicate with each other. Different type of connection for different type of unit Memory: consists of N words of equal length. Each word is assigned a unique numerical address (0,1,…,N-1). A word of data can be read from or written into memory. Input/Output : refer to each of the interface to an external device as a port and give each a unique address (e.g.,0,1,…M-1). There are external data paths for the input and output of data external device and I/O module may be able to send interrupt signals. Processor : reads an instruction and data, writes out data after processing, and uses control signals to control the overall system and also receives interrupt.

Chapter Two : Computer Function And Interconnection Computer Modules

Memory Connection Receives and sends data Chapter Two : Computer Function And Interconnection Memory Connection Receives and sends data Receives addresses (of locations) Receives control signals Read Write Timing

Input/Output Connection(1) Chapter Two : Computer Function And Interconnection Input/Output Connection(1) Similar to memory from computer’s viewpoint Output Receive data from computer Send data to peripheral Input Receive data from peripheral Send data to computer

Input/Output Connection(2) Chapter Two : Computer Function And Interconnection Input/Output Connection(2) Receive control signals from computer Send control signals to peripherals e.g. spin disk Receive addresses from computer e.g. port number to identify peripheral Send interrupt signals (control)

CPU Connection Reads instruction and data Chapter Two : Computer Function And Interconnection CPU Connection Reads instruction and data Writes out data (after processing) Sends control signals to other units Receives (& acts on) interrupts

Chapter Two : Computer Function And Interconnection Review…… CPU – executing program stored in memory by fetching one instruction at a time and executes it and then takes up next instruction. This action done repeatedly and known as instruction cycle. Computer consists of CPU, main memory, I/O and system interconnection. CPU consists of ALU, Control Unit, Registers and internal CPU interconnection. Interrupt is a signal or an event used to request the CPU to suspend the current program execution. Interrupt is a way to improve processing efficiency

NEXT….. Buses…..

Chapter Two : Computer Function And Interconnection Buses-Introduction Top level view : Computer consists of CPU, main memory and I/O. Connecting paths are necessary inside a computer between the subsystems (CPU, main memory and I/O) E.g: Instruction from memory to CPU. Data from memory to CPU and vice versa. Consists of multiple communication pathways, or lines. Each line capable of transmitting signals representing binary 1 and binary 0. Single and multiple BUS structures are most common e.g. Control/Address/Data bus (PC) e.g. Unibus (DEC-PDP)

What is a Bus? A communication pathway connecting two or more devices Chapter Two : Computer Function And Interconnection What is a Bus? A communication pathway connecting two or more devices Carrying information between the subsystems (CPU, memory and I/O) Usually broadcast Often grouped A number of channels in one bus e.g. 32 bit data bus is 32 separate single bit channels Power lines may not be shown PC consists of 3 different buses : data, address and control

1. Data Bus Provide a path for moving data between system modules. Chapter Two : Computer Function And Interconnection 1. Data Bus Provide a path for moving data between system modules. May consists of from 32 to hundreds of separate lines, number of lines refer to bus width and determines how many bits can be transferred at a time. The width of the data bus is a key factor in determine overall performance. WHY?

2. Address bus Identify the source or destination of data Chapter Two : Computer Function And Interconnection 2. Address bus Identify the source or destination of data e.g. CPU needs to read an instruction (data) from a given location in memory Bus width determines maximum memory capacity of system e.g. 8080 has 16 bit address bus giving 64k address space

Chapter Two : Computer Function And Interconnection 3. Control Bus Transmit both command and timing information between system modules. Timing signal indicate the validity of data and address information. Command signal specify operations to be performed. Memory write: data on bus to be written into the address location Memory read: data from the addressed location to be placed on bus I/O write: data on the bus to be output to the addressed I/O port I/O read: data from the addressed I/O port to be placed on the bus Transfer ACK: Indicate data has been accepted from or placed on the bus

Chapter Two : Computer Function And Interconnection Cont’d.. Bus request: indicates that a module needs to gain control of the bus Bus grant: indicates that a requesting module has been granted control of the bus Interrupt request: indicates that an interrupt is pending Interrupt ACK: Acknowledges that the pending interrupt has been recognized Clock: used to synchronize operations Reset: initializes all modules

Bus Interconnection Scheme Chapter Two : Computer Function And Interconnection Bus Interconnection Scheme

Physical Realization of Bus Architecture Chapter Two : Computer Function And Interconnection Physical Realization of Bus Architecture

Single Bus Problems Lots of devices on one bus leads to: Chapter Two : Computer Function And Interconnection Single Bus Problems Lots of devices on one bus leads to: Propagation delays Long data paths mean that co-ordination of bus use can adversely affect performance If aggregate data transfer approaches bus capacity Most systems use multiple buses to overcome these problems

Traditional bus*(ISA) (with cache) Chapter Two : Computer Function And Interconnection Traditional bus*(ISA) (with cache) SCSI-Small computer sys interface *reasonably efficient but begins to break down for higher performance is seen in the I/O devices. ----introduces mezzanine architecture ISA-’open’ design for PC bus by IBM

Chapter Two : Computer Function And Interconnection Multiple bus computer The communication inside computer system occurs over different types of buses Local bus System bus I/O bus Mezzanine bus Mezzanine architecture – high speed bus closely integrated with the rest of the system, requiring only a bridge between processor’s bus and high speed bus.

Chapter Two : Computer Function And Interconnection High Performance Bus

Bus Types Dedicated Multiplexed Separate data & address lines Chapter Two : Computer Function And Interconnection Bus Types Dedicated Separate data & address lines Multiplexed Shared lines Address valid or data valid control line Advantage - fewer lines Disadvantages More complex control Ultimate performance

Bus Arbitration More than one module controlling the bus Chapter Two : Computer Function And Interconnection Bus Arbitration More than one module controlling the bus e.g. CPU and DMA controller Only one module may control bus at one time Arbitration may be centralised or distributed

Centralised or Distributed Arbitration Chapter Two : Computer Function And Interconnection Centralised or Distributed Arbitration Centralised Single hardware device controlling bus access Bus Controller Arbiter May be part of CPU or separate Distributed Each module may claim the bus Control logic on all modules

Timing Co-ordination of events on bus Synchronous Chapter Two : Computer Function And Interconnection Timing Co-ordination of events on bus Synchronous Events determined by clock signals Control Bus includes clock line A single 1-0 is a bus cycle All devices can read clock line Usually sync on leading edge Usually a single cycle for an event Synchronous – the occurrence of events on the bus is determined by a clock.

Synchronous Timing Diagram Chapter Two : Computer Function And Interconnection Synchronous Timing Diagram

Asynchronous Timing – Read Diagram Chapter Two : Computer Function And Interconnection Asynchronous Timing – Read Diagram Asynchronous – the occurrence of 1 event on a bus follows and depends on the occurrence of the previous event.

Asynchronous Timing – Write Diagram Chapter Two : Computer Function And Interconnection Asynchronous Timing – Write Diagram

PCI Bus Peripheral Component Interconnection. Chapter Two : Computer Function And Interconnection PCI Bus Peripheral Component Interconnection. Acting as an intermediate bus between the sys. bus and I/O bus. High speed bus Isolates slow speed I/O subsystems from the processor. Brings I/O controller closer to the memory. Develop in 1990 for Pentium-based system and released all patents to the public domain. PCI may be configured as a 32 or 64 bit 49 mandatory signal lines.

Why PCI ??? High bandwidth Processor independent bus Peripheral bus Chapter Two : Computer Function And Interconnection Why PCI ??? High bandwidth Processor independent bus Peripheral bus Better system performance for high speed I/O systems Economically I/O requirements A few chips to implement and support other buses attached to it.

Example of PCI configurations Typical desktop system Chapter Two : Computer Function And Interconnection Example of PCI configurations Typical desktop system

Example: Typical server system Chapter Two : Computer Function And Interconnection Example: Typical server system

PCI Bus Lines (required) Chapter Two : Computer Function And Interconnection PCI Bus Lines (required) Systems lines : include the clock and reset pins Address & Data : include 32 lines that are time multiplexed for address and data. The other lines in this group are used to interpret and validate the signal lines that carry the address and data. Interface Control : control the timing of transactions and provide coordination among initiators and targets Arbitration : these are not shared lines and each PCI master has its own pair of arbitration lines that connect it directly to the PCI bus arbiter. Error lines : used to report parity and other error

PCI-mandatory signal lines System pins CLK, RST# Address & Data Pins AD[31::0], C/BE[3::0]#, PAR Interface control lines FRAME#, IRDY#, TRDY#,STOP#, IDSEL,DEVSEL Arbitration Pins REQ#,GNT# Error reporting pins PERR#, SERR#

PCI Bus Lines (Optional) Chapter Two : Computer Function And Interconnection PCI Bus Lines (Optional) Interrupt pins : provide for PCI devices that must generate requests for service. Each PCI device has its own interrupt line or lines to an interrupt controller. Cache support pin : these pins are needed to support a memory on PCI that can be cached in the processor or another device. 64-bit bus extension pin : include 32 lines that are time multiplexed for address and data and that are combined with the mandatory address/data lines to form a 64-bit address/data bus. Other lines in this group are used to interpret and validate the signal lines that carry the address and data. There are two lines that enable two PCI devices to agree to use 64 bit capability. JTAG/boundary scan pins : These signal lines support testing procedures define in IEEE stabdard 1149.1.

PCI Commands Transaction between initiator (master) and target Chapter Two : Computer Function And Interconnection PCI Commands Transaction between initiator (master) and target Master claims bus Determine type of transaction e.g. I/O read/write Address phase One or more data phases

PCI Read Timing Diagram Chapter Two : Computer Function And Interconnection PCI Read Timing Diagram

Chapter Two : Computer Function And Interconnection Bus Arbitration Process of determining the bus master who has the bus control at a given time when there is a request for bus mastership from one or more bus masters. When more than one bus master simultaneously needs the bus, only one of them gains control of the bus and become active bus master. The other would wait for their turn. The ‘bus arbiter’ decides who would become current bus master.

Chapter Two : Computer Function And Interconnection PCI Bus Arbiter

Chapter Two : Computer Function And Interconnection PCI Bus Arbitration

Lab Discussion elsif clk='1' and clk'EVENT then Q<=D; This statement says that if clk has a current value of 1 and if there has been an event on the clk line, assign Q the value of D LAB #3 : FINITE STATE MACHINE GUIDE FOR LAB #3