Computer System Structures I/O structure I/O hardware Isolated I/O ports Memory mapped I/O    Textbook Silberschatz, Chapter 2

General Purpose Computer System I/O Structure General Purpose Computer System Memory Controller A modern, general-purpose computer system consists of CPU number of device controllers They are connected through a common bus BUS also provides access to shared memory

Device Controllers The device controller is responsible for moving the data between the peripheral devices that it controls and the BUS. Each device controller is in charge of a specific type of device Many same type of devices can be connected through the same controller (SCSI, USB)

Information exchange The CPU and the device controllers can communicate directly and exchange information Between Device Controller and CPU registers. The CPU and the device controllers can execute concurrently, competing for memory access (Direct Memory Access to Memory by Device Controller). Memory controller’s function is to synchronize access to the memory.

The System Bus consists of buses Peripherial The system bus consists of 3 main groups of lines: Address Bus: Transfers the memory address or the device I/O port address Data Bus: Transfers the data between CPU registers, Memory and Device Controllers’ Registers. The data is accompanied with the Address. Control Bus: Signals on these lines show the availability or the direction of sending the Data or the Address. Many lines show the Availability or Absence of some events in the system.

I/O Hardware I/O methods Despite the incredible variety of I/O devices we need only a few concepts to understand how the devices are attached and how the software can control the hardware. There are two ways of information exchange between the host and I/O devices: Through the Isolated I/O ports Through the Memory Mapped I/O Ports Mainframes Use I/O special processors (Channels) The information exchange could be done using one of below methods by the software: Polling or programmed I/O Interrupts

I/O Ports How can the processor give commands and data to a controller to accomplish an I/O transfer ? The controller has one or more registers for data and for control signals. These registers (we call them I/O ports) could be accessed by unique addresses – I/O port addresses. The processor communicates with the controller by reading and writing bit patterns in these registers

General map of Isolated I/O Ports addresses for PCs

I/O Ports Data and Control An I/O port typically consists of 4 registers, called the (1) status, (2) control, (3) data-in (4) data-out

I/O Ports Control Register The Control Register can be written by the host to start a command or to change the mode of a device one of the bits could define the full-duplex or half-duplex communication another bit parity checking a third bit sets the word length to 7 or 8 bits other bits select one of the speeds supported by the serial port Put display in Alphanumeric or Graphical mode.

I/O Ports Status Register The Status Register contains bits that can be read by the host. These bits indicate states, such as whether the current command has completed, whether a byte is available to be read from the data-in register, and whether a device error has occurred.

I/O Ports Data Registers The Data-Input Register is read by the host to get the input data. f.e. the pressed key’s value from the keyboard   The Data-Output Register is written by the host to send output data. (f.e. LED’s value of keyboard – NumLock, ScrollLock, CapsLock.)

Isolated I/O Ports One way in which this communication can occur is through the use of special I/O instructions in al, 64h ;Read keyboard status register from 0x64 port. out 60h, al ;send the command to keyboard to port 0x60

Memory Mapped I/O The device-controller registers are mapped into the address space of the processor. The CPU executes I/O requests using the standard data-transfer (memory access) instructions to read and write the device-controller registers. The graphics controller has I/O ports for basic control operations but the controller has also a large memory mapped region to hold screen contents. The controller generates the screen image based on the contents of this memory.

Separate Video RAM Separate VRAM The address space is the same (main RAM’s address space But physically the Video RAM is placed in the Video Controller Does not take any amount of memory from the existing RAM Not Separated VRAM – You have 2GB memory – 0.5 GB is lost for VRAM Separated VRAM – You have 2GB memory + 0.5 GB VRAM

Dual Ported Video RAM Dual Ported Most forms of video RAM are dual-ported, which means that while the processor is writing a new image to video RAM the display is reading from video RAM to refresh its current display content.

MIPS Memory Mapped I/O 0xffff0000 input control register (only the two LSB’s are used) 0xffff0004 input data register (holds one byte) 0xffff0008 output control register (only the two LSB’s are used) 0xffff000c output data register (holds one byte)

MIPS Memory Mapped I/O Read and Write Data lui $t0, 0xffff lw $s2, 4( $t0) lui $t0, 0xffff sw $s2, 12( $t0 )

Memory Mapped I/O Advantage: This technique is simple and convenient to use. Moreover, writing millions of bytes to the graphics memory is faster than issuing millions of I/O instructions. Disadvantage: Because a common type of software fault is a write through an incorrect pointer to an unintended region of memory, a memory-mapped device register is vulnerable to accidental modification. Of course, protected memory helps to reduce this risk.