Acquisition systems VME-CAEN Focsaneanu Marin DFNA

Summary Standard VMA Data acquisition VMEbus components: VME Controller ADC QDC TDC CAENVMElib

VMEbus (VersaModular Eurocard bus) is a bus (computer data path) system Designed by Motorola Used in industrial, commercial, and military applications worldwide. Standard VME First of all I’m going to tell you what is a vme bus : VMEbuses are used in traffic control systems, weapons control systems, telecommunication switching systems, data acquisition, video imaging, and robots. VMEbus systems withstand shock, vibration, and extended temperatures better than the buses used in desktop computers, making them ideal for harsh environments.

Standard VME A VMEbus system is based on the VME standard. The VME standard defines the mechanical specifications such as: board dimensions connector specifications enclosure characteristics the electronic specifications signal functions timing signal voltage levels and master/slave configurations.

Data acquisition Functional unit called MASTER Master / slave architecture Functional unit called MASTER Functional unit called SLAVE Data Data acquisition is the process of sampling signals that measure real world physical conditions and converting the resulting samples into digital numeric values that can be manipulated by a computer. Data acquisition systems typically convert analog waveforms into digital values for processing.  A VMEbus system uses a master/slave architecture. A master is a device that controls another device. For example, a computer sends data to a printer. The computer is the master, and the printer is the slave because the printer cannot control the computer. A VMEbus system may have several master devices, which is why it is called a multiprocessing bus. A bus master is any device that can initiate transactions (read, write, Interrupt Acknowledge (IACK), BLT,and MBLT) on the bus. All CPUs are bus masters. In most cases, cards capable of being bus masters can also respond as bus slaves. A bus slave is any device that can respond to transactions within its Memory Window. All memory devices and most graphics devices are bus slaves. Initiates transactions Responds to transactions Since multiple Masters can reside on the bus, it is a MULTIPROCESSING bus

VME Components The VME data acquisition system consists of VME digitizer modules plugged into the VME backplane, controlled by master module. VME master module is a VME Optical Link Bridge to PCI (Peripheral Component Interconnect) Master module is controlled using a computer through an optical fiber cable.

VME Controller – V1718 VMEBus module The V1718 is a VME to USB 2.0 Bridge, housed in a 1-unit wide VME 6U module. The unit acts as a VME Master module  and can be operated from the USB port of a standard PC. The board can operate as VME System Controller

VME Controller the arbitration bus, the data transfer bus, As a system controller a VMEbus system has four sub- buses: the arbitration bus, the data transfer bus, the priority interrupt bus, and the utility bus. The arbitration bus controls the requests from various devices using an arbiter module. It gives permission to each device to use the bus and notifies requesting devices when the bus is busy. Requests are based on priority. The data transfer bus is used for reading and writing operations between modules. The priority interrupt bus handles interrupts and monitors the interrupt request lines, which range from interrupt request 1 to IRQ7. IRQ7 has the highest priority. The utility bus supports a system clock.

ADC CAEN V785N VMEBus module The Model V785 N is a 1-unit wide VME 6U module housing 16 Peak Sensing Analog-to-Digital Conversion(ADC)channels. The peak values are converted into voltage levels by the Peak Sensing sections and then multiplexed and converted by two fast 12bit ADC modules. The ADCs use a sliding scale technique

Peak sensing The peak detection is as shown in this simplified block diagram . The functioning of this circuit is based on : The gate and the clear signals that alows the charging and discharging of the c1 capacitor Througthout this process the signal is amplified and digitised by the 12-bit ADCs.

for better visualisation we have this timing diagram that includes different time ranges: idle, data acquisition, settling time, digitisation and clear. While the conversion logic is idle, the occurrence of a GATE pulse starts the acquiring data phase, until the first peak is reached. When this happens, the peak value is held by the capacitor C1 until the end of the digitisation which takes about 6 μs. After the digital conversion, the clear phase takes place which makes the conversion logic idle again.

Analog to digital conversion Sliding scale technique The output of each PEAK section is multiplexed, by group of 4 channels, and subsequently converted by two fast 12 bit ADCs, each of which operates the conversion on a group of 16 / 8 (depending on the version) channels The ADC section supports the sliding scale technique to reduce the differential nonlinearity This technique consists in adding a known value to the analog level to be converted, (thus spanning different ADC conversion regions with the same analog value. The known level is then digitally subtracted after the conversion) and the final value is sent to the threshold comparator.

QDC CAEN V792 N VMEbus module This model is a 1-unit wide VME 6U module housing 16 Charge-To-Digital Conversion channels (QDS) The integrated currents are converted into voltage levels by the QAC sections , multiplexed and converted by two fast 12-bit ADC modules.

TDC CAEN V1290 VMEbus module This module is a 32 channel Multihit Time-To-Digital Conversion (TDC), housed in a 1-unit wide VME 6U module.   TDC is a device for recognizing events and providing a digital representation of the time they occurred. In electronic instrumentation and signal processing, a time to digital converter (abbreviated TDC) is a device for recognizing events and providing a digital representation of the time they occurred.

The data acquisition can be programmed in "EVENTS" : TRIGGER MATCHING MODE CONTINUOUS STORAGE MODE.

TRIGGER MATCHING MODE match window window offset extra search margin A match between a trigger and a hit is detected within a programmable time window. The trigger matching control on the V1290 is handled through 4 programmable parameters  match window,  window offset,  extra search margin,  reject margin. match window window offset extra search margin reject margin.

CONTINUOUS STORAGE MODE In this readout mode the data loaded are straightly forwarded into the Readout FIFO. In this readout mode the data loaded are straightly forwarded into the Readout FIFO of the TDC and then loaded in the Output Buffer. All the hits received by the enabled channels are stored as valid data into the Output Buffer. The Time Origin (Time Zero) is represented by the latest RESET

CAENVMELib Library Open (Init) and Close the communication and the devices Caenvmelib is a set of functions for the control and the use of caen vme bridges. Tipicaly , it provides functions calls to: Open (Init) and Close the communication and the devices Make single Read/Write cycles Make Block Transfer Read/Write cycles Wait for an interrupt and make a IACK cycle

CAENVMELib Library Make single Read cycles Make Block Transfer Read/Write cycles

CONCLUSION The VME DAQ in the current form provides us with a powerful system because of the large number of parameters which can be acquired simultaneously and its ability to handle high event rates.

References: VME Data Acquisition System: Fundamentals and Beyond, Abhinav Kumar Bhabha Atomic Research Centre, Mumbai, March 2011. Development of data acquisition software for VME based systems, A. Kumar, A. Chatterjee, K. Mahata, K. Ramachandran, BARC, Mumbai, India, 2012. Nuclear lectures , Michigan State University What is vmebus basics tutorial, Ian Pool www.caen.it