Introduction to Programmable Logic Devices 12/31/2017 Introduction to Programmable Logic Devices John Coughlan STFC Technology Department Detector & Electronics Division

PPD Lectures 12/31/2017 Programmable Logic is a Key Underlying Technology for PP Experiments. First-Level and High-Level Triggering Data Transport (Networks) Computers interacting with Hardware (Networks) Silicon Trackers (Millions of Data Channels) Commercial Devices. Developments driven by Industry. Telecomms, Gaming, Aerospace, Automotive, Set-top boxes…. ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Particle Physics Electronics 12/31/2017 Particle Physics Electronics CMS Custom Electronics Chips ASICs ANALOGUE $$$ Rad Hard, Low Power CERN LHC ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Particle Physics Electronics 12/31/2017 Particle Physics Electronics CMS Custom Electronics Chips ASICs ANALOGUE $$$ Rad Hard, Low Power CERN LHC ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Electronics Rooms Trigger Systems. DAQ Systems. DIGITAL Custom Digital Processing Boards VME Bus Crates john.coughlan@stfc.ac.uk

Particle Physics Electronics 12/31/2017 Special Dedicated Logic Functions (not possible in CPUs) Ultra Fast Trigger Systems (Trigger Algorithms) Clock Accurate Timing Massively Parallel Data Processing (Silicon Trackers with Millions of Channels) Custom Designed Printed Circuit Boards PCBs. ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Commercial Programmable Logic Devices, FPGAs john.coughlan@stfc.ac.uk

CMS DAQ/Trigger Architectures 12/31/2017 CMS Fully custom PP ASICs Programmable Logic DIGITAL CPUs Commodity PCs ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time “Telecoms Network” ~ 1 Tbps john.coughlan@stfc.ac.uk

Lecture Outline FPGA Field Programmable Gate Array 12/31/2017 Programmable Logic Devices Basics Evolution FPGA Field Programmable Gate Array Architecture Design Flow Hardware Description Languages Design Tools ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Digital Logic Logic Gates 12/31/2017 ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Digital Logic Logic Gates Transistor Switches 12/31/2017 ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Transistor Switches john.coughlan@stfc.ac.uk

Digital Logic < 40 nm ! $$$ Logic Gates MOORE’S LAW 12/31/2017 Logic Gates MOORE’S LAW ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Transistor Switches < 40 nm ! $$$ john.coughlan@stfc.ac.uk

Digital Logic Black Box SUM of PRODUCTS Truth Table 12/31/2017 Black Box SUM of PRODUCTS Truth Table (Look Up Table LUT) Digital Logic Function 3 Inputs Product AND (&) Sum OR (|) ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Digital Logic Black Box SUM of PRODUCTS Truth Table 12/31/2017 Black Box SUM of PRODUCTS Truth Table (Look Up Table LUT) Digital Logic Function 3 Inputs Product AND (&) Sum OR (|) ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Digital Logic Black Box SUM of PRODUCTS Truth Table 12/31/2017 Black Box SUM of PRODUCTS Truth Table (Look Up Table LUT) Digital Logic Function 3 Inputs Product AND (&) Sum OR (|) ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Programmable Logic Devices PLDs 12/31/2017 Inputs SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC Un-programmed State ANDs Planes of ANDs, ORs ORs Outputs Logic Functions ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Programmable Logic Devices PLDs 12/31/2017 Inputs SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC Un-programmed State ANDs Planes of ANDs, ORs ORs Outputs Logic Functions ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Programmable Logic Devices PLDs 12/31/2017 Inputs SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC Un-programmed State ANDs Planes of ANDs, ORs ORs Outputs Logic Functions ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Programmable Logic Devices PLDs 12/31/2017 Inputs SUM of PRODUCTS (Re-)Programmble Links Reconfigurable GLUE LOGIC Un-programmed State ANDs Planes of ANDs, ORs ORs Outputs Logic Functions Sums ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Programmed PLD Product Terms john.coughlan@stfc.ac.uk

Programmable Logic Devices PLDs 12/31/2017 Logic Functions Programmed PLD Sums ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Product Terms john.coughlan@stfc.ac.uk

Programmable Logic Devices PLDs 12/31/2017 Logic Functions x x x Programmed PLD x x Sums ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Product Terms john.coughlan@stfc.ac.uk

Programmable Logic Devices PLDs 12/31/2017 GLUE LOGIC Logic Functions x x x x Programmed PLD x x x Sums ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Product Terms john.coughlan@stfc.ac.uk

Complex PLDs CPLDs Programmable PLD Blocks Programmable Interconnects 12/31/2017 CPLDs Programmable PLD Blocks Programmable Interconnects Electrically Erasable links Feedback Outputs CPLD Architecture ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Sequential Circuits 12/31/2017 Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory) Inputs ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Sequential Circuits 12/31/2017 Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory) Intermediate New Output every clock edge Inputs Register CLOCK ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time EDGES john.coughlan@stfc.ac.uk

Sequential Circuits 12/31/2017 Combinational Logic (Larger circuits difficult to predict) Synchronous Logic driven by a CLOCK Registers, Flip Flops (Memory) Intermediate New Output every clock edge Inputs Clock Rate determines speed Comb Logic Must meet Timing => Predictable circuits Register CLOCK ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Shift Registers, Pipelines, Finite State Machines … EDGES john.coughlan@stfc.ac.uk

Field Programmable Gate Arrays FPGA 12/31/2017 Field Programmable Gate Array ‘Simple’ Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for memory chips (Moore’s Law) A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible. john.coughlan@stfc.ac.uk

Field Programmable Gate Arrays FPGA 12/31/2017 Field Programmable Gate Array ‘Simple’ Programmable Logic Blocks Massive Fabric of Programmable Interconnects Standard CMOS Integrated Circuit fabrication process as for SRAM memory chips (Moore’s Law) Huge Density of Logic Block ‘Islands’ 1,000 … 100,000’s in a ‘Sea’ of Interconnects A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible. FPGA Architecture john.coughlan@stfc.ac.uk

Field Programmable Gate Arrays FPGA 12/31/2017 A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible. john.coughlan@stfc.ac.uk

Logic Blocks Logic Functions implemented in Look Up Table LUTs. 12/31/2017 Logic Functions implemented in Look Up Table LUTs. Flip-Flops. Registers. Clocked Storage elements. Multiplexers (select 1 of N inputs) ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time FPGA Fabric Logic Block john.coughlan@stfc.ac.uk

Look Up Tables LUTs 12/31/2017 LUT contains Memory Cells to implement small logic functions Each cell holds ‘0’ or ‘1’ . Programmed with outputs of Truth Table Inputs select content of one of the cells as output 3 Inputs LUT -> 8 Memory Cells 3 – 6 Inputs ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Static Random Access Memory SRAM cells Multiplexer MUX john.coughlan@stfc.ac.uk

Look Up Tables LUTs 12/31/2017 LUT contains Memory Cells to implement small logic functions Each cell holds ‘0’ or ‘1’ . Programmed with outputs of Truth Table Inputs select content of one of the cells as output Configured by re-programmable SRAM memory cells 3 Inputs LUT -> 8 Memory Cells 3 – 6 Inputs ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time Static Random Access Memory SRAM cells Multiplexer MUX john.coughlan@stfc.ac.uk

Logic Blocks 12/31/2017 Larger Logic Functions built up by connecting many Logic Blocks together ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Logic Blocks 12/31/2017 Larger Logic Functions built up by connecting many Logic Blocks together Determined by SRAM cells SRAM cells ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Clocked Logic Registers on outputs. CLOCKED storage elements. 12/31/2017 Registers on outputs. CLOCKED storage elements. Synchronous FPGA Logic Design, Pipelined Logic. FPGA Fabric Pulse from Global Clock (e.g. LHC BX frequency) ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time FPGA Fabric Special Routing for Clocks Clock from Outside world (eg LHC bunch frequency) john.coughlan@stfc.ac.uk

Input Output I/O Getting data in and out 12/31/2017 Input Output I/O Getting data in and out Up to > 1,000 I/O “pins” (several 100 MHz) john.coughlan@stfc.ac.uk

Input Output I/O Getting data in and out 12/31/2017 Input Output I/O Getting data in and out Up to > 1,000 I/O “pins” (several 100 MHz) Special I/O SERIALISERS ~ 10 Gbps transfer rates Optical TRx john.coughlan@stfc.ac.uk

Designing Logic with FPGAs 12/31/2017 Design Capture. High level Description of Logic Design. Graphical descriptions Hardware Description Language (Textual) ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Hardware Description Languages 12/31/2017 Language describing hardware (Engineers call it FIRMWARE) Doesn’t behave like “normal” programming language ‘C/C++’ Describe Logic as collection of Processes operating in Parallel Language Constructs for Synchronous Logic Compiler (Synthesis) Tools recognise certain code constructs and generates appropriate logic Not all constructs can be implemented in FPGA! 2 Popular languages are VHDL , VERILOG Easy to start learning… Hard to master! ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

VHDL ENTITY Declaration Input Output to Module (STD LOGIC) 12/31/2017 VHDL ENTITY Declaration Input Output to Module (STD LOGIC) SIGNALS Declaration WIRES CONCURRENT ASSIGNMENTS CONDITIONAL ASSIGNMENTS => MULTIPLEXERS john.coughlan@stfc.ac.uk

VHDL PROCESS Declaration. CONCURRENT functions. Synchronous Logic. 12/31/2017 VHDL PROCESS Declaration. CONCURRENT functions. Synchronous Logic. COMPONENT Declaration john.coughlan@stfc.ac.uk

Designing Logic with FPGAs 12/31/2017 High level Description of Logic Design Hardware Description Language (Textual) Compile (Synthesis) into NETLIST. Boolean Logic Gates. Target FPGA Device Mapping Routing Bit File for FPGA Commercial CAE Tools (Complex & Expensive) Logic Simulation Design Flow ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Designing Logic with FPGAs 12/31/2017 High level Description of Logic Design Hardware Description Language (Textual) Compile (Synthesis) into NETLIST. Boolean Logic Gates. Target FPGA Device Mapping Routing Bit File for FPGA Commercial CAE Tools (Complex & Expensive) Logic Simulation Design Flow ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Designing Logic with FPGAs 12/31/2017 High level Description of Logic Design Hardware Description Language (Textual) Compile (Synthesis) into NETLIST. Boolean Logic Gates. Target FPGA Device Mapping Routing Bit File for FPGA Commercial CAE Tools (Complex & Expensive) Logic Simulation Design Flow ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Configuring an FPGA 12/31/2017 Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory. Lose configuration when board power is turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. PROM or Digital Camera card Configuration takes ~ secs JTAG Port ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Configuring an FPGA 12/31/2017 Millions of SRAM cells holding LUTs and Interconnect Routing Volatile Memory. Lose configuration when board power is turned off. Keep Bit Pattern describing the SRAM cells in non-Volatile Memory e.g. PROM or Digital Camera card Configuration takes ~ secs JTAG Port Programming Bit File ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time JTAG Testing john.coughlan@stfc.ac.uk

Field Programmable Gate Arrays FPGA 12/31/2017 Large Complex Functions Re-Programmability, Flexibility. Massively Parallel Architecture Processing many channels simultaneously cf MicroProcessor Fast Turnaround Designs  Standard IC Manufacturing Processes. Moore’s Law  Mass produced. Inexpensive.  Many variants. Sizes. Features.  PP Not Radiation Hard  Power Hungry  No Analogue  A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible. john.coughlan@stfc.ac.uk

FPGA Trends State of Art is 40nm on 300 mm wafers 12/31/2017 State of Art is 40nm on 300 mm wafers Top of range >500,000 Logic Blocks >1,000 pins (Fine Pitched BGA) Logic Block cost ~ 1$ in 1990 Today < 0.1 cent Problems Power. Leakage currents. Design Gap CAE Tools ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Summary Programmable Logic Devices FPGA Field Programmable Gate Arrays 12/31/2017 Summary Programmable Logic Devices Basics Evolution FPGA Field Programmable Gate Arrays Architecture Design Flow Hardware Description Languages Design Tools Importance for Particle Physics Experiments john.coughlan@stfc.ac.uk

References The Design Warrior’s Guide to FPGAs 12/31/2017 References The Design Warrior’s Guide to FPGAs Clive Maxfield, Newnes Elsevier VHDL for Logic Synthesis Andrew Rushden, Wiley FPGA manufacturer web sites www.xilinx.com www.altera.com FPGA Online www.pldesignline.com www.fpgajournal.com www.doulos.com john.coughlan@stfc.ac.uk

12/31/2017 Spare Slides john.coughlan@stfc.ac.uk

System on a Chip Add Embedded Micro-Processor Cores in Fabric 12/31/2017 Add Embedded Micro-Processor Cores in Fabric e.g. RISC PowerPC Ethernet Interface Run Operating System e.g. Linux Combine Micro-Processor & Massively Parallel Logic Dual Design Flows Firmware HDL Software C ‘outline’ of coverage time-plan - What is an FPGA - And why are they important for HEP questions - any time john.coughlan@stfc.ac.uk

Time line of Programmable devices 12/31/2017 A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible. john.coughlan@stfc.ac.uk

Application Specific Integrated Circuits ASICs 12/31/2017 Prefabricated Programmed Custom Fabricated Design from Scratch Large Complex Functions . Millions of Gates Customised for Extremes of Speed, Low Power, Radiation Hardness (Very) Expensive to Design (in small quantities) > $1 Million mask set (Very) Hard to Design. Long Design cycles. NOT Reprogrammable. FROZEN in Silicon. High Risk Limited Complexity Thousands of Gates Cheap Easy to Design Reprogrammable. A field-programmable gate array (FPGA) is a large-scale integrated circuit that can be programmed after it is manufactured rather than being limited to a predetermined, unchangeable hardware function. The term "field-programmable" refers to the ability to change the operation of the device "in the field," while "gate array" is a somewhat dated reference to the basic internal architecture that makes this after-the-fact reprogramming possible. john.coughlan@stfc.ac.uk