Digital Design Lecture 14

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Presentation transcript:

Digital Design Lecture 14 ROMs and RAMs Mano, 7.6-7.8

PLD Configurations

An Example PLA Buffers provide true and complement of inputs XORs provide programmable complementors on outputs Similar to PROM Partial variable decoding Only some minterms

PLA Programming Table Table 7-5

Solution to Example 7-2 Implement F1(A,B,C)=(0,1,2,4)

Programmable Array Logic Fixed OR array Programmable AND array

PAL Fuse Map PAL Programming Table Table 7-6

Sequential PLDs

Sequential Programmable Devices Sequential (simple) programmable Logic device (SPLD) Field-programmable logic sequence (FPLS, defunct – too hard to use) Registered PAL / macrocell structure Complex programmable logic device (CPLD) Collection of SPLDs on a chip Field programmable gate array (FPLA) Logic blocks (look-up tables, multiplexers, gates, flip-flops) Programmable input/output blocks Programmable interconnections Microprocessor (using PROM)

Macrocell Logic

CPLD