Background Reading Chap 12.12, 13.7 Hall, Hall & McCall Chap. 6.2 I/O Power Delivery Background Reading Chap 12.12, 13.7 Hall, Hall & McCall Chap. 6.2 12/4/2002

Power Delivery Introduction In general power delivery analysis at the board level is very difficult. Determining the voltage at any point in time on an entire board is akin to predicting the weather. There are fairly good estimation methods for determining the effects of chip load, power planes, and capacitors. Determining effects of signaling on the board power becomes very complex. Chip manufacturers have reasonably good methods for determining the power delivery to the silicon from the board. This is only for a single chip. We will call this the traditional analysis The second and more interesting topic is the effect of I/O switching on chip power and vice versa. I/O Power Delivery 12/4/2002

Topics We will introduce the traditional methods first, then spend most of the time on I/O power delivery. The method we will talk about in the I/O power delivery section will be simple but illustrates some profound effects. Power delivery “noise” can create EMI which we will not cover. Robust treatment of power delivery is a great topic for research. One point to consider is that ideal power delivery is an impedance of 0 ohms between generation and utilization. Now consider that measuring impedances near 0 ohms has a number of challenges. Again another good topic for research. I/O Power Delivery 12/4/2002

Traditional Power Delivery Analysis The traditional method is basically evaluating the step response of the PDN (power delivery network) A simple outline of the simulation steps is as follows. Create system model May be reduced to simple RLC ladder. More complete analysis may use bed-spring models or S parameters. The die is divided into di/dt regions. In simulation place di/dt loads at the die regions with voltage controlled resistors driven by scaled current steps. Then evaluate waveform regions of the largest specified step response This analysis is usually focused on the charge cycle. The high di/dt creates a demand. We need to measure how well the rest of the PDN works to stabilize the voltage. This is done by evaluating each droop and then trying to associate it with each PDN design domain. I/O Power Delivery 12/4/2002

Example of Simple Traditional Method We just look for droops and spike on the delivered power rail Regulator Board High current di/dt ~ amps/microsecond I/O Power Delivery 12/4/2002

Resonance Traditional analysis does not comprehend feedback and interaction between data switching and PDN resonance. The di/dt are aggregate responses from silicon blocks of relatively uncorrelated switching of millions very small transistors. I/O buffers are large, have high power demand, and are synchronized in time. We will start the story with the I/O signaling I/O Power Delivery 12/4/2002

Hypothetical Signaling J X X X I/O Signal at receiver pin I/O Signal at receiver pad Received I/O signal I/O Power Delivery 12/4/2002

Ideal I/O Signal Threshold Levels I/O Power Delivery 12/4/2002

Ideal Receiver Output Received I/O signal IO signal @ pad I/O Power Delivery 12/4/2002

What happens if power does this once in a while? Power Story What happens if power does this once in a while? Vss Rail X Vcc Rail I/O Power Delivery 12/4/2002

Power Noise Can Cause Missed Data Received I/O signal 0.7v 3.3v ov ov IO signal @ pad Results in Transient Failure I/O Power Delivery 12/4/2002

Assignment 3 extra credit: Show Power Noise Can Cause Signal Distortion Vdie Use circuit at the right Find the value of Cdie that limits the ripple to 10% (peak to peak) Plot the impedance vs. frequency looking out of node Vdie for the solution I/O Power Delivery 12/4/2002

I/O Signal – Power Dependence Can this cause this? data Vcc Yes! I/O Power Delivery 12/4/2002

I/O power for Intel® Pentium® processor GTL+ Circuit Modeling History: I/O power for Intel® Pentium® processor GTL+ Just used L*di/dt and capacitive droop (traditional method) New signaling presents additional power issues I/O Power Delivery 12/4/2002

Pentium® 4 Buffers – On die termination Need to keep power rail stiff Die Die Board Board Required for transmission line signal integrity I/O Power Delivery 12/4/2002

On Die Termination – Drawbacks and Solution Watts! Very high instantaneous current demand Package transmission lines cause very high speed return currents Solution: Add on-die I/O power capacitance. Die Board I/O Power Delivery 12/4/2002

Estimating I/O Power Delivery Impact Concept building Example I/O Power Delivery 12/4/2002

Package Caps Do not always exist! Define Power Domains Mid Tier Caps Die Caps VRM Package Caps Do not always exist! Package Bulk Caps I/O Power Delivery 12/4/2002

Simple Concept : Keep buckets filled I/O Power Delivery 12/4/2002

Keep this flow in mind Increasing frequency content VRM It’s tempting to view this circuit analysis backward – more later I/O Power Delivery 12/4/2002

Buckets (capacitors) are filled at different rates, by different paths Fill rates are different Lower frequencies apply as path gets closer to VRM Transmission line return is a high speed path High speed path and low speed path may be different. Low frequencies disperse over larger areas Conclusion: Can analyze return path and I/O power delivery (PD) independently There are caveats I/O Power Delivery 12/4/2002

Overall Response of PD is Simple: Method: cascade resonant tank circuits A tank circuit is just an LC network Insight from PD with tank analysis E.g. what really matters Challenge: Reduce circuit for simple analysis … 90% solution “End game” – use more sophisticated tools … better accuracy I/O Power Delivery 12/4/2002

Inductance between die and package Die to Package Stage VRM Inductance between die and package Die Cap Note: Inductance includes series resistance (ESR) capacitance includes series inductance (ESL), resistance (ESR) I/O Power Delivery 12/4/2002

Package to Mid-Tier Stage VRM Inductance between package and mid-tier cap Package Cap I/O Power Delivery 12/4/2002

Inductance between mid-tier and bulk cap Mid-Tier to Bulk Stage VRM Inductance between mid-tier and bulk cap Mid Tier Cap I/O Power Delivery 12/4/2002

Inductance between bulk cap to VRM (including VRM L) Bulk to VRM Stage VRM Inductance between bulk cap to VRM (including VRM L) Bulk Cap I/O Power Delivery 12/4/2002

Example Concept of squares for estimation Develop some real values Determine sensitivities Draw some conclusions I/O Power Delivery 12/4/2002

Estimating L from a “square” Power Plane Power Pins Separation Power Cap Pads Ground Plane Let separation =20 mils = 1.75 sq Draw Guide lines ½ sq (2 sq in ||) ¼ sq (4 sq in ||) 1 sq L=32 pH/mil separation /sq L= 32 ph *20*1.75 L= 1.12 nH Estimate an average cross-sectional power delivery line I/O Power Delivery 12/4/2002

In this example we will analyze all the buffers on a bus. Scaling In this example we will analyze all the buffers on a bus. We will use the parameter “Ndriver” to indicate how many buffers are on a given bus (all on one power rail) I/O Power Delivery 12/4/2002

Example Values – “Die2Pkg” Rough Scaled Guess L pH via L= 32 . mil_separation sq N vias . C = C N die drivers The may be some number of vias (“Nvias”) that connect the chip power to the package power. Lvia is the inductance we will use for each via. All the vias are in parallel so the equivalent inductance of the network is just Lvia divided by Nvia Ndrivers is the number I/O buffers. All the Cdie capacitors are in parallel and thus the equivalent capacitance is just the sum of all the die capacitors. I/O Power Delivery 12/4/2002

Example Values – “Die2Pkg” 40 vias @ 0.5nH/Via + pH 1 32 * 50 pH sq *120 m m Plane separation = . mil sq 4 88 drivers @ 100 pF/driver = 88 drivers @ 100 pF/driver = 8.8 nF Better Guess –> 3 D Field Solver I/O Power Delivery 12/4/2002

Model of Capacitor and Terminology ESR: Equivalent Series Resistance ESL: Equivalent Series Inductance C: Capacitance I/O Power Delivery 12/4/2002

Example Values – “Pkg2Mid” Rough Guess Scaling Equations L= 32 pH mil_separation sq . L via N vias C= C cap Cap The will likely be some number of vias (“Nvias”) that connect the package power to the board power. Lvia is the inductance we will use for each via. All the via are in parallel so the equivalent inductance of the network is just Lvia divided by Nvia Ncap is the number of mid tier caps. All the package capacitors are in parallel and thus the equivalent capacitance is just the sum of all the package capacitors. I/O Power Delivery 12/4/2002

“Pkg2Mid” parameter assignment 15 mil separation, ½ sq Two 2.2 mF IDC package caps ESL = 80 pH ESR = 100 mW 20 Vias at 0.7 nH/via C = 4.4 mF ESL = 40 pH ESR= 50 mW L = 275 pH Real capacitor Better Guess –> 3 D Field Solver I/O Power Delivery 12/4/2002

Example – “Mid2Bulk” Rough Guess VRM 15 mil separation, 3 sq pH L= 32 VRM . mil_separation sq . C= C N cap Cap 15 mil separation, 3 sq Fifteen 0.1 mF caps ESL= 500 pH ESR= 0.6 W L = 1.4 nH C = 1.5 mF ESL = 33 pH ESR = 40 mW I/O Power Delivery 12/4/2002

Example - “Bulk2VRM” Rough Guess VRM C 1000 mF ESL = 250 pH L = 1 nH 32 . mil_separation sq . C= C N cap Cap C 1000 mF ESL = 250 pH L = 1 nH 15 mil separation, 2 sq Two 500 mF caps ESL=500 pH I/O Power Delivery 12/4/2002

Example Used for Analysis die2pkg pkg2mid mid2bulk Vddp L6 L5 L3 50ph 275p 0/1V 1.4n 7n + 200 MHz .05 ESR .04 B - .0003 ESR DieR 0.15 ESR A 33pH 8.8nf 40ph ESL Cdie ESL .250nh ESL 4.4uf Assignment 4 – Use PSpice to plot impedance vs. frequency (1 KHz – 1GHz) looking from A and then B Cpkg 1.5uf 1000uF C board C Bulk Actually, any spice simulator can do this I/O Power Delivery 12/4/2002

Estimate frequency response in MathCAD Define functions Define constants and frequency array I/O Power Delivery 12/4/2002

Parallel Circuit function MathCad Functions Parallel Circuit function Capacitor function Inductor function I/O Power Delivery 12/4/2002

Define Components Parameters for PDN circuit {}bu corresponds to the bulk capacitor {}md corresponds to the mid tier capacitor {}pk corresponds to the package capacitor {}die corresponds to the I/O die power decoupling {}2{} corresponds to inductance between two respective regions Zdie(f) convert the capacitor to a usable impedance verse frequency. I/O Power Delivery 12/4/2002

Building a circuit with threading Start at the bulk cap and thread the circuit inward to the die Zbulk is the impedance associated with the bulk resistance, impedance of the capacitance, and the impedance of the inductance I/O Power Delivery 12/4/2002

Examine Results of Zin vs. Frequency Notice the peaks and the values of impedance I/O Power Delivery 12/4/2002

Power Impedance Looking Outward From Die to VRM from simulation Note: DV = Z *Di 186 MHz Resonance 1 0.1 Ohms 0.01 0.001 0.1 1 10 100 1000 MHz Review: Zero ohms is ideal! I/O Power Delivery 12/4/2002

Look in Time Domain: 500 MHZ Digital Data Power Rail 0.1 1 10 100 0.01 MHz Ohms 1000 0.001 I/O Power Delivery 12/4/2002

Look in Time Domain: 186 MHZ Digital Data Power Rail 0.1 1 10 100 0.01 MHz Ohms 1000 0.001 I/O Power Delivery 12/4/2002

Let’s see what happens when package caps are removed. VRM I/O Power Delivery 12/4/2002

Now Look What Happens in Frequency Domain 1 Without package cap 0.1 Ohms With Package cap Impedance at 200MHz is lower. If the Data rate is 200MHz the power noise may actually be reduced! 0.01 0.001 0.1 1 10 100 1000 MHz I/O Power Delivery 12/4/2002

Lets vary 200 MHz in the time domain Digital Data Power Rail 0.1 1 10 100 MHz Ohms 1000 0.01 0.001 I/O Power Delivery 12/4/2002

Now Look What Happens at 100 MHZ Digital Data Power Rail 0.1 1 10 100 0.01 MHz Ohms 1000 0.001 I/O Power Delivery 12/4/2002

Not the resonance (remember “backwards” from earlier?) What is important? Critical Resonance On-die cap and inductance to next cap Plus ESL of that cap Die Cap Not the resonance (remember “backwards” from earlier?) I/O Power Delivery 12/4/2002

Other Factor – Return Path Non TEM or … Anywhere a signal return is not a transmission line … e.g. boundaries Pins Anti-vias Effect is to increase inductance to either power or ground circuit. Need 3-D tools to evaluate Mutual coupling is important Plane shape may have its own resonance I/O Power Delivery 12/4/2002

Scale to total drivers – N drivers N Coupled Tlines on package We need to add an extra scaled load to simulate data with I/O power delivery. If not, we need to scale the entire power driver for the number of buffers in the simulation. On Die Power Delivery package Pkg Cap Mid Cap Bulk Cap VRM Scale to total drivers – N drivers N Coupled Tlines on package Package Return path I/O Power Delivery 12/4/2002

Key Takeaways I/O PD is part of signaling solution space On die decoupling may introduce PD resonance issues Follow I/O PD guidelines if you don’t have detail chip data Modeling Use info from frequency domain to seed time domain simulation Still need to do L*di/dt and droop work too 2 Level approach to I/O power model First: estimates based on L per square. Next: refine w/ 3-D modeling Return path modeling Evaluate at boundaries I/O Power Delivery 12/4/2002

Summary Power variations can be data sensitive New technology many require new PD analysis I/O power resonance is “die outward “not “die inward”. Frequency analysis is important for I/O PD PD can be merged into I/O simulations Higher frequencies will require us to explore more higher order effects. Take I/O decoupling guideline seriously I/O Power Delivery 12/4/2002

Assignment 5: MathCad Power Calculator Create plot with all the caps and inductors doubled Embedded MathCad OLE I/O Power Delivery 12/4/2002