Last upgrade R&D results on the LPC works ATLAS/LPC group meeting (2014 February 13) Roméo Bonnefoy and François Vazeille ● Three talks given at the last Tile upgrade meeting of February 7th. https://indico.in2p3.fr/conferenceDisplay.py?confId=9811 - Upgrade developments in Clermont-Ferrand (François Vazeille, 10 mn). - Performances of the HV system out of Drawers (François Vazeille, 25 mn). - The FATALIC project: progression and schedule in 2014 (Nicolas Pillet, 20 mn). ● Four R&D tasks: - Handling tools of Mini-Drawers. - Active Dividers. - High Voltage regulation system out of Drawers (LPC option). - Very Front End/Front End electronics based on custom-made ASICs (LPC option). ● Today, only a summary with additional comments about the collaboration behavior.  A good illustration of the true life in instrumentation !

Roméo Bonnefoy, Guy Savinel, Pierre Verdier Handling tools of Mini-Drawers Roméo Bonnefoy, Guy Savinel, Pierre Verdier and François Vazeille ●New Slider and new Basket tested at CERN in November 2013 - Slider #3 and Basket #2 according to the observations made at CERN. Mainly: ▪ Slider: made longer in order to be aligned on more Girder Rings. ▪ Basket: better access to Mini-Drawers and easier handling. - In 3 Tilecal Module positions in the Building 175: 0°, 45°, 90°.

More Girder Rings in contact Slider at 45° Slider at 90° Contact screws in the Finger to set the effort to the Finger (and not to the Girder Rings) More Girder Rings in contact 3

Basket in position Several accesses to the PMT Blocks Insertion of the Drawers

● Minor new modifications to do: edges less “cutting” in the manipulations. ● Next meeting  Detailed protocol on the handling of tools in various situations in ATLAS.  The same approach would be welcome in the Barcelona developments. ● These tools will be available for the first Demonstrators.

Active Dividers ● New delivery of Dividers for the ATLAS restart Roméo Bonnefoy, Christian Fayard, Romano Marino, Marie-Lise Mercier, Dominique Pallin, Eric Sahuc, Timothée Theveneaux-Pelzer, Eric Sahuc and François Vazeille ● New delivery of Dividers for the ATLAS restart  Last week, 78 Dividers (With QC sheets). Comment: the repairs/certifications of the Dividers are made at LPC. ● Radiation tests - Neutron irradiations: made in September 2013 at VALDUC (CEA).  The analysis will be reported to Tilecal during the next weeks. - Gamma irradiations: will be made at Argonne.  Test bench demonstration to Gary Drake for Argonne tests. (December2013: the humidity prevented the demonstration).

VFE and FE electronics ● 3 R&D in progress in 2 steps, Roméo Bonnefoy, Baptiste Joly, Christian Fayard, Marie-Lise Mercier, Dominique Pallin, Nicolas Pillet and François Vazeille + 2 other engineers in µelectronics ● 3 R&D in progress in 2 steps, with defined milestones and tests at CERN ◊ Step 1: Use of existing chips for tests of a single channel  2014-Q2 - 3in1 Prototype card with FATALIC3 chip +TACTIC1 chip. - Main Board with numerical integration (1 card). ◊ Step 2: Design, production and tests of FATALIC4  2014-Q4 - 3in1 with FATALIC4 chip (3 ADCs inside) (48 cards). - Evolution of the Main board for FATALIC4 (4 cards).

● Step 2: FATALIC 4 (3 TACTICs + 1 for tests)  Selection of 2 outputs: - Medium Gain and Low Gain. - Medium Gain and High gain.

MB-2 DB ● Step 2: Main Board and 3in1 for FATALIC4 Production DACs VFE-ASIC VFE-ASIC VFE-ASIC VFE-ASIC VFE-ASIC VFE-ASIC ASIC FATALIC4 (3 ADC) MB-2 Input 3 channels x 2 gains CLK & x 12 bits + 1 sel @40 Mbits/s CTRL Transfer to DB in LVDS 4x280Mbit/s Data digital integration to : 3 channels x 16 bits Max 10kHz Input 3 channels x 2 gains CLK & x 12 bits + 1 sel @40 Mbits/s CTRL Transfer to DB in LVDS 4x280Mbit/s Data integration to : 3 channels x 16 bits Max 10kHz FPGA-A0 FPGA-A1 o/e Receiver FPGA-A : XILINX KINTEX 7 DB LASER DRIVER Data digital integration to : 3 channels x 16 bits Max 10kHz Transfer to DB in LVDS 4x280Mbit/s Input 3 channels x 2 gains CLK & x 12 bits + 1 sel @40 Mbits/s CTRL FPGA-B : XILINX KINTEX 7 Data integration to : 3 channels x 16 bits Max 10kHz Transfer to DB in LVDS 4x280Mbit/s Input 3 channels x 2 gains CLK & x 12 bits + 1 sel @40 Mbits/s CTRL o/e Receiver FPGA-B0 FPGA-B1 Regulators VFE-ASIC VFE-ASIC VFE-ASIC VFE-ASIC VFE-ASIC VFE-ASIC Production of 4 cards (1 Super-Drawer) PM PM PM PM PM PM

Serial SYNC Control CLK Readout Data Flow in FPGA for 1 channel FPGA : Cyclone IV SLVS OUT CLK LHC SYNC IN 40MHz Fitting DB working SLVS To Daughter Board To 3in1 Board Serial 2x280Mbit/s Reg ADC Middle Gain 12 12 Reg ADC Middle Gain 12 2xLVDS 12 + Demux - 2x @40Mbit/s LVDS 12 Offset ADC Middle Gain 12 Serial SYNC Control CLK LVDS @80Mbit/s Serial 2x280Mbit/s Reg ADC H/L Gain 12 12 Reg ADC H/L Gain 12 2xLVDS 12 + - H/L GAIN H/L GAIN Offset ADC High Gain 12 Mux Digital integration 12.7 ms max ,in steps of 0.1 ms 16 2 Serial (I2C) 12 Offset ADC Low Gain 12 3x12 Control (SPI) 4 REG DAC Inject 3in1 4 16 2 INJECTION ORDER 1 part per PMT 3 part per FPGA 1part per FPGA Common for 3 PMT DEFAULT SIGNALS ARE LVCMOS

the HV system out of Drawers Performances of the HV system out of Drawers Roméo Bonnefoy, Robert Chadelas, Christian Fayard, Marie-Lise Mercier, Eric Sahuc and François Vazeille WARNING: All the concurrent options are based on the present Tilecal design made by LPC (But for the commercial option … too much expensive).

● HV R&D story ◊ Tilecal upgrade meeting 10 Nov 2009 3 FV talk from a study with Robert Chadelas and Daniel Lambert  6 Options: 3 On Drawers 3 Out of Drawers 1 4 2 5 ◊ Tilecal upgrade meeting 1 Feb 2013 3 1 4 FV: Only 2 (3) solutions are realistic  LPC Will look at Option 3 (4). 2 5 GD: Only 1 solution is possible  Noise aspects in the Options 3/4

● Reminder of the basic principles ◊ General constraints - HV distribution towards Mini-Drawers (Maximum of 12 HV channels). - HV performances similar to the present ATLAS conditions: they are better than the initial specifications of HV stability ≤ 0.5 V. - Possibility of individual HV channel switching. - Improved HV safety (Dust, metallic pieces, humidity, hazards…). - Increased radiation levels. ◊ Specific principles of the studied option - Regulation system in USA15 using the same electronics schemes. - Distribution of the individual HVs via Multiconductor cables. - Passive HV bus cards. Permanent access to the electronics and reliability. Full insensitivity to radiations. Cheap. ◊ R&D requested, - In particular the regulation and noise aspects. - If validated  HV supply for the Demonstrator in Building 175.

● Set-ups CERN - The set-up is the same in the tests made at LPC Clermont-Ferrand and in the building 175 at CERN. - The same components are used also (HV crate, cables, HV bus cards, FE parts).

HV Bus boards (no active components) 12 channels. A 4-layer printed circuit: External layers as shielding, Internal layers to distribute the HVs. - Noise killers (1K) everywhere. HV regulation crate: ¼ of the total space (4 Modules later) Rear HV outside HV cards on special supports The LV/HV supplies. Channel ordering. recovery. LV’s inside LV DCS HV Source Front CANBUS

● Some words about the HV Opto cards Some story! ▪ Historically, the first design (Scheme 1) of the HV Opto card had no transistors outside the Optocouplers of the regulation loop. ▪ The first campaign of radiation tests showed the sensitivity of Optocouplers:  gain losses at the 2 Opto sides: Opto and Transistor  regulation failures at a certain radiation level. 1 5 MOC8204 Opto side Transistor and HV side 2 6 4 ▪ The solution (Scheme 2) was to “boost” the 2 sides by putting Transistors  New scheme.  New radiation/qualification tests.  Satisfying working of the HV system (well demonstrated by Tilecal data) but regulation loop more sensitive to the environment (Cable lengths, etc.).

Scheme 1 Scheme 2 - In this R&D study, the 2 schemes are compared, because there are no longer radiation concerns. - The best one will be chosen to measure the whole performances.

● Four types of measures HV noise measures. HV regulation measures. HV Drop measures. PMT/LED/full HV set-up signal measures. The most expected results ! Comment: Noise expected higher (How much ?) … but not too much ! - Every time Transistors ( gains) are concerned in the comparisons  noise is expected to be increased. A priori there are 2 concerns: - The HV Opto Scheme 2/Scheme 1 - The Active Dividers/Passive Dividers - When the cables are longer.

● Several campaigns of tests Because of the low noises, it is difficult to reproduce everywhere/every time the same environment. Example: Changing the sector mains of the various elements (HV and LV supplies, scope) can affect the results. After a time consuming learning phase of several months,  Tests made in 6 periods: LPC 2013 November 19-21 CERN 2013 November 25-27 LPC 2013 December 18-19 LPC 2014 January 24-25 LPC 2014 February 3-4 LPC 2014 February 11

● Tested combinations A big number of combinations ! ▪LV inside HV crate (Switching) ▪LV outside HV crate (Linear) ▪1.52 m ▪20 m (4) ▪100 m + 4 lengths of Internal cables ▪HV Bus inside Bench ▪HV Bus outside Bench BUS BUS BUS BUS ▪Load ▪Passive Divider ▪Active Divider ▪HV Opto Scheme 1 ▪HV Opto Scheme 2 without/with load ▪HV LPC1 ▪HV LPC2 ▪HV Tilecal 2 sites: all combinations ▪ LPC Clermont-Ferrand ▪ Building 175 CERN

● Conclusions ◊ A lot of combinations have been tested  The simplest scheme is the best solution: Scheme 1 (No Transistors in the regulation loop).

◊ It is satisfying fully the Tilecal specifications: - Very low noise level: below 2.5 mV in any set-ups  Relative value < 0.0025/700 = 3.6 106. ▪ Minimum noise pick up at the HV Bus board  Design. ▪ Independent from the cable length. - Regulation performances: Stability < 0.1 mV (From Loic in ATLAS ~ 0.1 mV) - Insensitivity to radiations, humidity, dust and mechanical damages (Falling pieces, handling) [See talk in Tilecal maintenance weekly meeting about present HV Bus cards]. - Suppression of 3 Finger LVPS Bricks or 3 Voltage Regulators. - Possibility of cheap and safe individual channel switching, using straps. - Permanent access to the electronics  100% working of all channels - Likely a "cheap" solution … but a realistic estimate must be made.

It is not a Back up solution ◊ New developments are foreseen (See Back up slides) + contribution to the next Expert week at CERN (March)

◊ The present prototype can be used (as it is) to supply a Demonstrator in the Building 175 - The four 20 m long cables are in place. - A whole HV Bus set is at CERN. - Minor changes must be made on the regulation crate (Fans, front Patch Panel…). - Standard DCS is operational and can be connected to the existing DCS. HV Prague HV LPC1 The 4 cables are routed HV crate

BACK UP

Hello Francois In order to do a mini demonstrator of the cable carriers, we needed to put a sort of slider, like yours. There is one dimension I don't have, I would appreciate very much if you could send me your CAD file of the slider or at least one critical dimension for us now, as I did not measure it. I need it urgently, sorry for the inconvenience Many thanks for your help Cheers Ferran

● Next developments ◊ Missing measures to make: noise versus applied HV Till now: at 700 V. Next: range 600-800 V. Made yesterday (see Back up slide) ◊ Optimisation of the Patch Panel routing  One of the outlined questions during the meeting.  We have a solution ! … that we will report soon.

◊ Optimization of the scheme Improvement of the HV bus cards at the Noise Killer level ▪ Noise Killers in the opposite side conditioned by existing connectors going though the printed circuits. ▪ If not available: Stiff coat or small plastic covers. Individual channel switching: As the individual channel failures are rare  Individual straps could be a simple, safe and cheap solution since the access to the crate is permanent. Decision of the “re-use” of the HV cards (long sizes, special PCB as supports and channel organization) or a new making by optimizing the sizes and without special supports. Optimization of the LV Power supplies inside the regulation crate.

Noise variation with respect to the applied HV (Realistic set up: 100 m long cable, Active Divider, LV supply inside the regulation crate) The measures at 700 V were made before the CERN meeting (February 3). The measures at 550 and 850 V were made after (February 11). Bruit RMS (mV) HV (Volts) Very coherent results, despite the different dates and difficulty of measures. At the upper HVout limit, the ratio noise/HVout is 2.6 10-3. Linear noise variation with respect to HVout within the allowed range of 300 V.  (noise) = 0.0024 (HVout)