Fundamentals of Nanoelectronics

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Presentation transcript:

Fundamentals of Nanoelectronics

ECE 4140/6140 Instructor: Avik Ghosh (ag7rq@virginia.edu) E315 Thornton (434-243-2347) Class: MWF 11-11:50 (THND222) HWs due: F beginning of class Office hrs/Tutorial: Thursday evenings Grader: Dincer Unluer (du7x@virginia.edu) Course

General Information on Matlab http://its.virginia.edu/research/matlab/ 1) For students who want to install a copy on their personal computers (need to use the UVAnywhere to start-up Matlab) http://its.virginia.edu/research/matlab/download.html#student 2) For students that want to use the Hive (Virtual Computers with Matlab installed that you can remote login using your personal computer). http://its.virginia.edu/hive/ 3) Use the stack computers.

Course website http://people.virginia.edu/~ag7rq/4140-6140/13/courseweb.html

Text/References VIrginia NanOComputing (VINO) www.nanohub.org VIrginia NanOComputing (VINO) http://www.ece.virginia.edu/vino

Grading info Homeworks Wednesdays 25% 1st midterm ~Feb end 20% 2nd midterm ~Mar end Finals ~May start 35%

Ch 9 (Atom to Transistor) Syllabus Ch 1 (Overview) 3-4 lectures Ch 2 (Schrodinger eqn) 4 lectures Ch 3 (SCF) 2-3 lectures 1st midterm (Feb end) Ch 4 (Bandstructure) 2-3 lectures Ch 5 (Subbands) 2-3 lectures Ch 6 (Capacitance) 2 lectures 2nd midterm (Mar end) Ch 7 (Level broadening) 3 lectures Ch 8(Coherent Transport) 3 lectures Ch 9 (Atom to Transistor) 2 lectures Ch 10 (Coulomb Blockade) 2 lectures Final (May start)

Ch1: The need for microscopic understanding of transport

The Device Researcher’s bread and butter Source Drain Gate Channel

The Device Researcher’s bread and butter Field effect transistor (FET) Source/Drain Contacts – very conductive Channel – limits resistance of FET Gate – controls resistance of FET

Why study transistors? Many chemical, biological and physical processes involve digital switching with various gates spin memories closed open ion channel switches (Mackinnon, Nature ’03) Molecular motors Biosensors

What would we look at in an FET? S-D Current ID Source-Drain Voltage Saturation S-D Current ID Turn-on Rise Gate Voltage What’s the physics behind these curves? (HW2) What about current along z direction?

The driving force behind microelectronics Moore’s Law: double # FETs/chip in 1.5 years

How far can we scale transistors? New physics emerges at these lengthscales

Cramming more transistors onto a chip Shorter time for electron to move across channel More memory elements on a chip Cheaper

Smaller, Faster, Cheaper

From Ralph Cavin, NSF-Grantees’ Meeting, Dec 3 2008

Silicon transistors already at nanoscale ! Intel’s 2003 transistor 6 nm MOSFET Bruce Doris, IBM 0.7 nm thick MOSFET Uchida, IEDM 2003 Smallness  quantum effects Quantum confinement Atomistic fluctuations Leakage, Tunneling Quantum Scattering

A major problem: Power dissipation! (HW1) New physics needed – new kinds of computation

Heat is a Burning problem!

How can we push technology forward?

Better Design Multiple Gates for superior field control (Intel’s Trigate/FinFET)

Better Materials?

Hard to align into a circuit! The material ‘zoo’ !! Silicon Nanowires (Low m < 100 cm2/Vs) 5 nm Organic Molecules ? (Reproducibility/ Gateability) 2 nm CNTs (m ~ 10,000cm2/Vs) Hard to align into a circuit! VG VD INSULATOR DRAIN SOURCE I < 10 nm Strained Si, SiGe (m ~ 270cm2/Vs) Bottom Gate Source Drain Top Gate Channel 15 nm

Graphene Atomistic Models Concept Physics Nobel, 2010 Architecture Drain Source Channel Gate Architecture Concept Physics Nobel, 2010

New Principles? Metallic spintronics already exists! GMR (Nobel, 2007) Harness electron’s spin “Spintronics” Multiferroics, Nanomagnetism Metallic spintronics already exists! GMR (Nobel, 2007) MRAMs

How can we model and design today’s devices?

Pushing the simulation envelope.. Bulk Solid (“macro”) (Classical Drift-Diffusion) ~ 1023 atoms Bottom Gate Source Channel Drain Clusters (“meso”) (Semiclassical Boltzmann Transport) 80s ~ 106 atoms Quantum corrections to classical concepts, usually experimentally motivated (e.g. Quantum Resistance, Quantum interference, etc) Problem: Cannot derive Quantum concepts from Classical equations !!! (e.g. Entanglement in quantum Computation) Molecules (“nano”) (Quantum Transport) Today ~ 10-100 atoms

Bottom-Up instead of Top-Down Bulk Solid (“macro”) (Classical Drift-Diffusion) ~ 1023 atoms Bottom Gate Source Channel Drain Clusters (“meso”) (Semiclassical Boltzmann Transport) 80s ~ 106 atoms Classical Concepts do come out of Quantum Mechanics Phase Breaking Events (“Decoherence”) Molecules (“nano”) (Quantum Transport) Today ~ 10-100 atoms

Bottom-Up instead of Top-Down Bulk Solid (“macro”) (Classical Drift-Diffusion) L > 1 mm Clusters (“meso”) (Semiclassical Boltzmann Transport) L ~ 100s nm Classical Concepts do come out of Quantum Mechanics Phase Breaking Events (“Decoherence”) Molecules (“nano”) (Quantum Transport) source drain L ~ 10 nm

The challenge: Quantum effects = Ohm’s Law NO MORE! Fourier’s Law NO MORE! R independent of material, geometry R = h/2q2 = 12.9 kW RQ independent of material, geometry k = p2kB2T/3h = 0.95pW/K R < R1 + R2 ! Fano Interference in QDs

The challenge: Atomistic effects Nanotube Data Williams group, UVa Characterizing single molecular traps using noise patterns (UCLA)

Back to familiar I-Vs What does a device engineer look for? Saturation S-D Current ID Turn-on S-D Current ID Rise Gate Voltage Source-Drain Voltage What does a device engineer look for?

Gate Dependence (Transfer Characteristics) Subthreshold Swing (mV/decade) Vd=0.5 Vd=1 DIBL (mV/V) S-D Current ID Gate Voltage Turn-on VT small to lower power dissipation S small to lower power dissipation (> 60 at room temperature) ON-OFF ratio high (bit error rate in logic) Low OFF current (static power dissipation) DIBL low (OFF current)

Drain Dependence S-D Current ID Source-Drain Voltage Mobility S-D Current ID Source-Drain Voltage Output conductance Want high mobility (high ON current  Faster switching) Want high output impedance (reliability)

How do we understand/model these IVs? Saturation S-D Current ID Turn-on S-D Current ID Rise Gate Voltage Source-Drain Voltage HW2

Starting point: Band-diagram Solids have energy bands (Ch 5) How do we locate the levels?

Filled levels  Photoemission hn S + hn  S+ + e-

Empty levels  Inverse Photoemission hn S + e-  S- + hn

Level separations  Optical absorption hn S  S* + hn

E Filling up the Bands with Electrons Empty levels Filled levels Metal (Copper) (charges move) Semiconductor (Si) (charge movement can be controlled) Insulator (Silica) (charges can’t move)