Top level chip assembly TDCpix Top level chip assembly S. Bonacini CERN PH/ESE/ME sandro.bonacini@cern.ch

Full chip floorplan 20.400x12.030 sq.mm Pixel matrix 20.400x12.030 sq.mm Top assembly with automatic P&R tools No synthesis at top level Chip finishing in full-custom tools Add chipring Re-route bandgap reference voltages Pad placement 196 total wirebond pads 158 south (i/o and power) 8 west (test pads) 8 east (test pads) 22 staggered power pads “South bank”

Hybrid pixel ASICs classification Chip Name Technology Year Pixel Size [um] Pixel Array Pixel Operation Bits/Pixel Data Type Start readout Acquisition Trigger Readout Output data port TDCpix (NA62) IBM 130n 2013 300 45*40 TOA and TOT 48 0-suppresed Data driven Continuous No 4 CML @ 3.2 Gbps ToPIX (PANDA) 2012 100 116*110 1-LVDS @ 312.4 Mbps Timepix3 55 256*256 PC and iTOT TOA 37 1,2,4 or 8-LVDS DDR @ 640 Mbps VeloPix PC 36 @ 4.8 Gbps EIGER UMC 250nm ~2009 75 4, 8 or 12 Full frame External 32-bit CMOS DDR @ 200 Mbps Medipix3RX 1,6,12 or 24 1,2,4 or 8-LVDS @ 250 Mbps Timepix IBM 250n 2006 PC, TOT or TOA 14 Non-continuous 32-bit CMOS @ 100 Mbps SmallPix (Q4) 35-40 384*384 512*512 24-32 0-compressed ClicPix_demo TSMC 65nm 2012 (Q4) 25 64*64 TOT and TOA 9 Non- 1 or 2-LVDS Alice1LHCb 2001 50*425 256*32 TOA and Binary 2 FIFO of 8 bit BCO Yes 32-GTL @ 40 Mbps PSI46 (CMS) 2005 100*150 52*80 Analog ? 6-8 bit analog @ 40 MHz FEI3 (ATLAS) 50 *400 160*18 8-bit TOA + address EOC event Buffering FEI4 (ATLAS) 2011 50*250 336*80 @ 320 Mbps Dosepix 2010 220 16*16 TOT 256 Semi-Continuous 1-CMOS @ 10 Mbps HEP Trigger-less Imaging HEP Low Rate HEP Triggered PH-ESE Seminar 8th May 2012 Dosimetry Courtesy of X.Llopart

South bank floorplan calibration pulse fanout TDC (x20) qchip (x4) Digital macros Timing description available Qchip TDC cal_fanout dll_clk_fanout SLVS Rx/Tx Analog macros (no timing description) Pixel matrix Bandgaps (analog, digital, temperature) Serializers+PLL Customized I/O pads & supply pads calibration pulse fanout TDC (x20) qchip (x4) config space & DLL clock fanout BG Serializer & PLLs BGs Staggered pads Staggered pads

Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Clocks & Power 7 power supply nets / ground nets For a total of 120 pads of which 22 staggered On floorplan gnd/vdd_digital1_2 (8 pad pairs + 5 staggered) default for connection to GND/VDD pins and TieLow / TieHigh gnd/vdd_analog1_2 (14 pad pairs + 4 staggered) gnd/vdd_tdc1_2 (7 pad pairs + 2 staggered) gnd/vdd_temp (1 pad pair) Direct connection to pads (no floorplan) gnd/vdd_pll (2 pad pair) gnd/vdd_serializer (12 pad pairs) I/O pad supply/ground gnd/vdd_slvs1_2 (5 pad pairs) 14 clock roots 2 input pads clk_dig (320 MHz) clk_dll (320 MHz) 12 generated by internal PLL Sx_CLK_FIFOread (40 MHz) Only goes to qchip Sx_CLK_multiserial (480 MHz) Sx_CLK_sync (320 MHz) Sinks are qchip and TDC. Top-level clock trees are relatively simple More complex distribution in sub-blocks top-level core standard-cell area filled with decoupling capacitors ~16000 DECAP_SB cells for a total of 3.8 nF …more in the sub-blocks Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

Custom pads No bridge, open VDD, GND bridge bridge, VDD, GND connected Enlarged MA connection to 60um for lower resistance Longer landing pad for wirebond & probing: 200um Not for staggered & lateral pads Break VDD and GND connections at both sides For power domain separation A bridge cell is added to connect VDD and GND DVSS, DVDD are common to all pads (no breaker) No bridge, open VDD, GND bridge bridge, VDD, GND connected GND VDD Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

Pads and power distribution TDCs MA power lines from pixel matrix, TDC 300um pitch next slide MA power lines from pads 73um pitch (no power ring) Test pads Staggered power pads Serializer

Pads and power distrib. (zoom) TDCs MA power lines from pixel matrix, TDC 300um pitch E1 horizontal lines 6x25 um MA power lines from pixel matrix, TDC 300um pitch Overlap region MA power lines from pads 73um pitch (no power ring) Test pads Staggered power pads Serializer MA power lines from pads 73um pitch

Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Verification Timing verification Static Timing Analysis (STA) Run on all digital sub-blocks Run on top level with timing information extracted from sub-blocks Post-layout Verilog simulation with annotated timing Full-chip simulation (Matt) Power distribution verification IR drop analysis Simulated IR drop in all digital sub-blocks “paper and pencil” verification for top level (Gianluca and Jan) Physical verification Design Rule Check (DRC) passes with waivers Layout vs Schematic (LVS) passes. Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

Justification for waiver DRC waiver list Groundrule Description of Rule Design Manual Value Requested Value Justification for waiver GR655b DV width. >= 28 20 bump bond pad opening GRQCAP1c (QY+HY) area (maximum per chip) (mm2). <=2,000,000 2,150,000 this total area of mim cap capacitors is neccesary for proper functionality of the pixel matrix GRMA946b DV(touching MA) terminal pad width (parallel to the closest CHIPEDGE) (must be rectangular). >=62 26/octagonal shape or opening in wide bars (bias connection for the detector) special shape and dimensions for bump bonding GRESD01 ALL IO (not including power supply pads) pads must be connected to one ore more RX n+ satisfying ESD01a and…. no ESD protection for bump bonded pads (inputs of the front end amplifier) because noise requirerments of the circuit GRESD01a HBM down diode minimum perimeter. >=110 GRESD01b HBM up diode minimum perimeter. >=220 GRMA945b DV(touching MA) must be within CHIPEDGE (maximum) (entire DV shape). <=150 bump bond pad matrix distributed over entire area of the chip - in total 1840 bump bonding pads front end chip connected to sensor by bump bonding technique GRMA946g DV(touching MA) terminal pad length (perpendicular to the closest CHIPEDGE) (increasing the dimension perpendicular to CHIPEDGE does not impact the pitch). >=95 octagonal pad for bump bonding Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch

Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch Status Status Design is submitted for fabrication DRC clean (with some waivers) LVS match Timing and power verified Sandro Bonacini - PH/ESE - sandro.bonacini@cern.ch