Lecture 3 Static properties (VTC and noise margins) The CMOS Inverter Lecture 3 Static properties (VTC and noise margins)

Where are we? OUT IN Inverter OUT IN Logic gates P N N-type Pull-down network P-type pull-up network OUT IN Logic gates P N Designing w switches Hands-on lab session 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Where are we? 1 Inverter OUT IN Logic gates Designing w switches 1 Inverter N-type Pull-down network P-type pull-up network OUT IN Logic gates Designing w switches Hands-on lab session 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Where are we? 1 Inverter OUT IN Logic gates Designing w switches Inverter N-type Pull-down network P-type pull-up network OUT IN Logic gates Designing w switches Hands-on lab session 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Where are we? VSW Inverter OUT IN Logic gates IDS Designing w switches N-type Pull-down network P-type pull-up network OUT IN Logic gates IDS Designing w switches Hands-on lab session 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

MOSFET I/V Characteristics IDS ON Saturation: IDSN=IDSAT,N IDSN=GONVDS VDS OFF: IDS=0 OFF: IDS=0 IDSP=GONVDS Saturation: IDSP=IDSAT,P ON 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

MOSFET I/V Characteristics IDS ON Saturation: IDSN=IDSAT,N Saturation: ISDP=IDSAT,P ON ISDP=GONVSD IDSN=GONVDS VDS OFF: IDS=0 OFF: IDS=0 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

MOSFET I/V Characteristics IDS ON Saturation: IDSN=IDSAT,N Saturation: IDSP=IDSAT,P IDSN=GONVDS VDS OFF: IDS=0 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

VIN/VOUT voltage plane VDD, VDD VDD NMOS OFF NMOS VIN VDD PMOS OFF PMOS 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

VIN/VOUT voltage plane VDD, VDD VDD NMOS OFF PMOS OFF VIN VDD 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Voltage Transfer Characteristic - VTC VOUT Inverter VDD, VDD VDD NMOS OFF PMOS OFF IDS,P=0 1 IDS,N=0 VDS IDS VIN VDD The ON p-switch pulls the output high 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Voltage Transfer Characteristic - VTC VOUT 1 Inverter VDD, VDD VDD NMOS OFF PMOS OFF IDS,P=0 IDS,N=0 IDS VIN VDD The ON n-switch pulls the output low VDS 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Voltage Transfer Characteristic - VTC VOUT Inverter VDD, VDD VSW VDD NMOS OFF PMOS OFF VSW IDS VSW VDS IDS Saturation: IDSP,N=IDSAT,P VIN VDD Switching occurs in the green region where both MOSFETs are saturated! And saturation currents are equal: Solving for VIN using x=kN/kP yields 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Voltage Transfer Characteristic - VTC DV VOUT Inverter VDD, VDD VSW VDD NMOS OFF PMOS OFF VSW IDS VSW VDS IDS Saturation: IDSP,N=IDSAT,P VIN VDD The switching voltage equation can be rewritten on a form easier to grasp if we introduce 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Voltage Transfer Characteristic - VTC VOUT Inverter VDD, VDD VSW VDD NMOS OFF PMOS OFF VSW IDS VSW VDS IDS VIN VDD Equal currents in top blue region yields VOUT vs. VIN! 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Voltage Transfer Characteristic - VTC VOUT Inverter VDD, VDD VSW VDD NMOS OFF PMOS OFF VSW IDS VSW VDS IDS VIN VDD Equal currents in bottom blue region yields VOUT vs. VIN! 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

The voltage characteristic (VTC) VOUT For x=kN/kP=1 we have What if we make n-channel MOSFET wider, i.e. for x>1? VDD What happens to VTC? Will switching voltage VSW increase or decrease? Assume x=4 and we have Assume x=1/4 and we have VIN VTN VSW VDD+VTP VDD 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

The voltage characteristic (VTC) VOUT Which VTC is NAND and which VTC is NOR? VDD NAND NOR VIN VTN VSW VDD+VTP VDD 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

The voltage characteristic (VTC) VOUT How about current flow? No current flow in red regions! ”short-circuit” current ISC flows in blue/green regions n-channel MOSFET saturated for VIN<VSW VDD p-channel MOSFET saturated for VIN>VSW VIN VTN VSW VDD+VTP VDD 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

MCC092 IC Design - Lecture 3: The Inverter Noise Margins- NML VOUT VOUT VIL,max VIH,min VDD Valid ”0” VIN Valid ”1” VDD Valid ”0” Valid ”1” VOH,min VOL,max NMH VIN not valid VIN VIH,min VIL,max 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

MCC092 IC Design - Lecture 3: The Inverter Noise Margins- NML VOUT VDD VIN VDD Valid ”1” VOH,min VIH,min VIN not valid Valid ”1” NML VIL,max VOL,max Valid ”0” VIN VIL,max VIH,min VOUT 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Memory cell characterization Butterfly Diagram VOUT VDD Valid ”1” VOH,min NMH Memory cell characterization VIN VOUT NML VOL,max Valid ”0” VIN VIL,max VIH,min 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Noise Margins – skewed inverters NMH NML NML NMH 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Noise Margins – an example NMH=VOH,min-VIH,min NML=VIL,max- VOL,max Let´s define valid regions from points where slope AV = -1! VOUT These points yields numbers for (VOH,min, VIL,max) and (VOL,max, VIH,min) so that NMH and NML can be calculated! VDD Valid ”0” Valid ”1” VIL,max VIH,min VOH,min VOL,max VIN VDD 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Noise Margins – an example NMH=VOH,min-VIH,min NML=VIL,max- VOL,max NMH=VOH,min-VIH,min1.12-0.68=0.44 V NML=VIL,max- VOL,max = 0.52-0.08=0.44 V Let´s define valid regions from points where slope AV = -1! VOUT 0.28 V DV=0.64 V These points yields numbers for (VOH,min, VIL,max) and (VOL,max, VIH,min) so that NMH and NML can be calculated! VDD Valid ”0” Valid ”1” DV/8 VOH,min For x=1, VTN=0.28 V and VTP=-0.28 V we have VSW=0.28+0.64/2=0.60 V and DV=0.64 V DV/8 Formulas can be derived (for x=1): VOH,min=VDD-DV/8=1.12 V VOL,max = DV/8=80 mV VIL,max=VSW-DV/8=0.52 V VIH,min=VSW+DV/8=0.68 V Formulas can be derived (for x=1): VOH,min=VDD-DV/8 VOL,max = DV/8 VIL,max=VSW-DV/8 VIH,min=VSW+DV/8 VOL,max VIN VIL,max VIH,min VDD 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

MCC092 IC Design - Lecture 3: The Inverter Summary CMOS inverter – schematic Voltage transfer characteristics (VTC) How to calculate switching voltage VSW Understand VSW dependence on kN/kP Understand switching current (ISC) flow Noise margins NMH and NML Butterfly diagram Match current curves 2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Why not n-switches in pull-up networks? Initial value before switch is turned ON: VOUT=0 Register cell VDD Adder cell p-switch Logic “one” VIN VOUT VOUT VDD   IDS Equivalent circuit: GND VOUT VDD VOUT=VDD-VTN   2017-09-05 MCC092 IC Design - Lecture 3: The Inverter

Why not p-switches in pull-down networks? Initial value before switch is turned ON: VOUT=VDD Register cell VDD Adder cell p-switch Logic “zero” VIN VOUT GND VDD VOUT VSS VOUT VDD   IDS Equivalent circuit: VOUT=-VTP   2017-09-05 MCC092 IC Design - Lecture 3: The Inverter