Resistor Transistor Logic - RTL Chapter 5 Resistor Transistor Logic - RTL

Resistor Transistor Logic The resistor Transistor Logic family is a family of logic gates that are made exclusively of resistors and transistors. The basic gate in every family is the inverter. The inverter is used to study the basic behavior of the logic gates. More complex gates are analyzed only to point out differences in behavior. The basic RTL inverter is the same as the BJT inverter we mentioned earlier.

The RTL Inverter VOH = VCC VOL = VCE (Sat) VIL = VBE (FA) VCC RC Vout RB Vin Vout VCC

RTL Inverter VTC V out V OH = VCC VOL = VCE (SAT) V IL = VBE (FA) V in

The RTL NOR Gate An RTL NOR gate can be made by replicating the Base resistor and the transistor in parallel for each input V CC R C V out R R R B1 B2 BN Q Q Q 1 2 N V V V IN1 IN2 INN

The RTL NOR Gate (Contd) Ideally, the RB for all inputs is the same and the BJTs are matched (identical). In this setup, the current through RC is the sum of all of the collector currents for the transistors:   The output voltage is Vout = VCC - IRC * RC

Operation of the RTL NOR Gate If all inputs are low, then all transistors are cut off and all Ici are 0. Therefore: Vout = VCC (VOH ) If any input is high, then that transistor will be in Saturation and Vout = VCE (Sat) (VOL) Therefore, the circuit implements the NOR function.

The RTL NAND Gate If the transistors are stacked instead of being in parallel, the result is a NAND Gate: As in the NOR gate, Vout = VCC- IRC * RC If any input is low, then that transistor will be cutoff. Therefore, its collector current Ici = 0. But given that: Ici = Iei-1 and Ici @ Iei Then all collector and emitter currents will be 0 and IRC = 0. Therefore, Vout = VCC (VOH )

V out R B1 IN1 Q 1 B2 IN2 2 BN INN N C CC The RTL NAND Gate If all inputs are high, then each of the transistors becomes saturated and Vout = N * VCE (Sat) (VOL) Therefore, the circuit implements a NAND gate. NOTE: Each higher transistor will require a higher input voltage to reach saturation. This is due to the emitter of the higher transistor being connected to the collector of the transistor below it. This makes the maximum number of inputs for the RTL NAND Gate very limited.

The RTL NAND Gate Fan-in Fan-in is the maximum number of inputs that a gate can have and still maintain proper functionality. The fan-in for an RTL NAND gate is limited by the fact that the output low voltage VOL needs to be low enough for a load gate to recognize it as low.

The RTL NAND Gate Fan-in (Contd) Consider the following setup: For the RTL inverter VIL = VBE (FA) So, for the multi-input NAND gate to function correctly, its output low voltage must be smaller than VBE (FA) V V CC CC R R C C V out R B Q R B1 Q 1 V IN1 R B2 V IN2 Q 2 R BN V INN Q N

The RTL NAND Gate Fan-in (Contd) However, from the above circuit, we have: VOL = N * VCE (Sat) So: N * VCE (Sat) < VBE (FA) or Assume, VCE (Sat) = 0.2 V and VBE (FA) = 0.7 V N  0.7 / 0.2  N  3.5 Therefore, the maximum number of inputs for an RTL NAND gate is 3

R B Q C V CC B1 1 C1 out B2 2 C2 BN N CN I RC RTL Fan-out

RTL Fan-out – Output Low We always consider the driving gate. When VIN of the driver is HIGH, its Vout = VCE(Sat) Given that VCE (Sat) < VBE (FA) Then all load transistors will be cut-off Therefore, IB1 = IB2 = … = IBN = 0 = IIL So, the low state does not affect fan-out.

RTL Fan-out – Output High When VIN of the driver is LOW, the transistor Q is cut-off and Vout = VCC However, Vout is the VIN for each of the load transistors. Therefore, Q1, Q2, …, QN will all be saturated and taking current into their bases. This will cause a non-zero IRC to flow. and Vout = VCC - IRC * RC

RTL Fan-out – Output High (Contd.) Since IRC = N * IB then, the more gates connected to the output the bigger IRC becomes and the smaller Vout becomes. The limit on Fan-out is when Vout drops all the way down to VIH. At that point Q1, Q2, …, QN are at the edge of saturation. Adding more gates will drive the transistors out of saturation. Maximum Fan-out occurs when Vout ≥ VIH

RTL Fan-out – Output High (Contd.) and IRC = N * IBi  Solving for N, we get

RTL Fan-out – Output High (Contd.) At maximum Fan-out, Vout = VIH. Substituting in the above formula we get:

RTL Fan-out Example Assume: Therefore, N = 12 VCC = 5 V, RB = 10 KW, RC = 1 KW, bF = 25, VBE(Sat) = 0.8 V, and VCE (Sat) = 0.2 V Therefore, N = 12

RTL Power Dissipation ICC (OL) Then For the output to be low, the transistor must be saturated. This makes the transistors of all load gates go into cut-off. The result would be that Iout = 0. Then R B C V CC I out + - CE (Sat) in is High

RTL Power Dissipation (Contd) ICC (OH) For the output to be high, the transistor must be in cut-off mode. That makes IC = 0. However, all load transistors will be in saturation and drawing current. Iout = N * IB To simplify the calculation, we need to come up with an equivalent circuit for the loads. R B C V CC I out Off in is Low = 0

RTL Power Dissipation (Contd) Replacing each of the saturated load transistors with a battery of value VBE(Sat), we get the equivalent circuit on the right. The circuit can further be simplified by recognizing that all of the RB's of the load gates are in parallel and can be replaced by a single RB/N. R' B V BE (Sat) R C CC

RTL Power Dissipation (Contd) Calculating the current, we get Where N is the number of loads

RTL with Active Pull-up To improve the fan-out of RTL gates, an active pull-up configuration is added to the output. This configuration increases the amount of current that the gate can supply on its output and therefore increases the fan-out. What is "active pull-up"? The output section of the basic RTL inverter is made up of a simple resistor (as shown on the right). This configuration produces a small, limited amount of output current. R C V CC out

RTL with Active Pull-up Keeping in mind that load gates look like capacitors with respect to the source gate, a large amount of current is needed to charge these capacitors. To increase the "sourcing" output current, we can replace the simple resistor with the "emitter follower" combination shown on the right. R C V CC out

RTL with Active Pull-up The "active pull-up" increases the gate's ability to "source" output current. This helps when the output is high. To improve the gate's ability to "sink" current in the low state, an "active pull-down" combination (like the one shown below) is also needed. V out

RTL with Active Pull-up Putting the circuit together, we get: R BS C CP V CC out Q P O S BP BO in Active Pull-Up Active Pull-Down

The RTL Inverter with Active Pull-Up RCP is always chosen to be much smaller then RC (about an order of magnitude smaller). This produces a large collector current for QP, which will produce a large emitter current which means a large Iout. RBO and RBS are chosen to be equal so that QO and QS turn on and off at the same time. Qs and its RBS are the simple RTL inverter from before. The output of this combination is the inverse of the input to the circuit. Since this output is the input of QP and the input of the circuit is the input of QO, then QP and QO will never be on at the same time.

The inverter's operation VIN QS QP QO Vout HIGH Sat. Off VCE (Sat) LOW F. A. VCC – VBE(FA) R BS C CP V CC out Q P O S BP BO in

Fan-out of RTL with Active Pull-Up Similar to the case for Basic RTL, when Vin is high, Vout = VCE(Sat)  IIL = 0. Therefore, the high state will determine the fan-out When Vin is low: QS is cut-off, QO is cut-off and QP is Forward Active, the output is high. When this output is connected to a similar gate, QS and QO of the load gate will be saturated and its QP will be off.

Fan-out of RTL with Active Pull-Up The load gate can be simplified into: However, since RBS and RBO are the same, we can simplify the load gate even more R' BS BO V BE (Sat) R' B / 2 V BE (Sat)

Fan-out of RTL with Active Pull-Up Connecting many load gates, we get the combination on the right. This can be further simplified into the circuit below: R' B / 2 V BE (Sat) R' B / 2N V BE (Sat)

Fan-out of RTL with Active Pull-Up Combining the circuit, we get: R' B / 2N V BE (Sat) R C CP CC out BP F. A. IEP N * I’IH

Fan-out of RTL with Active Pull-Up IEP = N * I’IH Assuming IEP  ICP, Solving for N: Maximum fan-out occurs when Vout = VIH If we use typical values, we get a fan-out of about 55.

Summary of RTL Discussion Pros: RTL is a very simple logic family using only a few simple elements to make up the logic gates RTL has a very good high noise margin (NMH). The RTL Power Dissipation is acceptable. Cons: RTL has a very small low noise margin (NML). The RTL NAND gate suffers from a very small fan-in. RTL has a small and limited fan-out. This makes it not very suitable for wide use. RTL utilizes a number of resistors. Resistors take a large area on an IC to manufacture. This makes RTL non-economical for IC manufacturing.