R4.21 – Public Report on "Scilab/Scicos code generation for IFP platform and real-time multicore code generation with SynDEx" Simon Nivault, Yves Sorel (INRIA), Rodolphe De la Rubia, Nicolas Pernet (IFPEN) March 2012

Deliverable short description: Overview INRIA / IFPEN collaboration INRIA: SynDEx software for optimized real-time scheduling and code generation for distributed heterogeneous architecture IFPEN: xMOD model integration tool for co-simulation The goal is to obtain a real-time execution of a set of simulators (simulator = model + fixed step solver) onto a multicore PC architecture. The input is a set of models: Scicos models or Simulink Top-level graph of interconnected models (including Dymola or AMESim imported models) The distributed scheduling and the corresponding executive code are provided by SynDEx The execution is launched in the xMOD tool, providing instrumentation and experiment lab support as usual, SynDEx providing efficiency of the multicore execution This deliverable corresponds to the implementation of the specification R4.8 An improved version of the tool chain including documentation will be delivered at M39

Deliverable short description: starting point SynDEx: SynDEx is a system level CAD software based on the AAA methodology (Algorithm Architecture Adequation). Adequation means an efficient mapping of the algorithm application onto the architecture. Indeed, the implementation of an algorithm onto an hardware architecture corresponds to a real-time scheduling as well as a resources allocation problem. SynDEx solves this difficult problem statically and generates distributed deadlock free code with low executive overhead. Missing functionality: SynDEx handles different types of processor, microcontroller, point-to-point link and buse via dedicated code generation SynDEx executive kernels. Nevertheless, no existing kernel handles multicore architecture, specially on Windows (for prototyping) and RTX (for real-time execution). xMOD-HiL: xMOD combines at the same time, a heterogeneous model integration environment, as well as a virtual instrumentation and experimentation laboratory. Model integration means co-simulation of several interconnected simulators. xMOD-HiL stands for a specific execution mode of xMOD where simulators runs in real-time, mainly to by able to interact with real components in a Hardware-in-the-Loop approach. Missing functionality: xMOD co-simulation kernel is multi-thread and already reaches satisfying performance on Windows for non real-time simulation. However, xMOD-HiL is based on the RTX operating system for real-time simulation and the user has to manually distribute the tasks among the cores. For large simulation, this is not an acceptable solution: xMOD-HiL need an external tool to optimize and generate an efficient distribution and scheduling of the task set.

Delivrable short description: Composition SynDEx is a downloadable as a freeware (www.syndex.org), designed and developed at INRIA Paris - Rocquencourt Research Center France, by the AOSTE team. That team added the optimized code generation feature for multicore PCs on Windows and RTX (no xMod). The corresponding executive kernels will be distributed at the end of the project on the SynDEx web site. xMOD HiL is developed by IFPEN and distributed by D2T. Both xMOD modification in order to launch the generated code from SynDEx and the SynDEx code generation feature dedicated to xMOD are confidential materials. Consequently, the public part of the deliverable consists in the present PowerPoint presentation and a movie: The presentation describes the achieved work on the two tools, SynDEx and xMOD, The movie presents the use of the obtained tool chain.

Needed developments: tasks decomposition T1: Update of the Scicos/SynDEx gateway to the last releases of both tools (INRIA) T2: Extension of the Scicos/SynDEx gateway in order to be able to transform blocs including Modelica description (INRIA) T3: Improvement of the macro code generation for SHM (INRIA) T4: RTX/Windows multi-core code generation with SynDEx (INRIA) T5: xMOD multi-core code generation with SynDEx (INRIA/IFPEN) T6: Automatic transformation of Simulink Superblock graph to a SynDEx algorithm and code generation for each Superblock (IFPEN) T7: Test and Validation (IFPEN) T8 : Tool chain documentation (INRIA/IFPEN) 7 8 1 2 3 4 6 5 will be delivered at M39 (deliverable R4.29)

T1: Update of the Scicos/SynDEx gateway to the last releases of both tools (INRIA) The Scicos/SynDEx gateway provides a way to convert a Scicos model into a SynDEx algorithm. This gateway relied on an old version of both tools. The Scicos/SynDEx gateway mechanisms were updated to allow conversion of models of the last ScicosLab version (4.4) into algorithms for last version of SynDEx 7 This work mainly consisted in the gateway adaptation to the new mechanisms of Scicos graph flattening and clock calculi.

T2: Extension of the Scicos/SynDEx gateway in order to be able to transform blocs including Modelica description (INRIA) Difficulties to handle Modelica parts without a strong effort from the Scicos team: This team finally did not join the project Will be certainly not fixed in OpenProd This risk was early identified but it is not a blocking issue: IFPEN existing models in Modelica fails to be simulated using the Modelica compiler of Scicos (which does not entirely implements the language) IFPEN existing (heterogeneous, including Modelica) models can be translated to SynDEx via RTW solution

T3: Improvement of the macro code generation for SHM (INRIA) SynDEx was already able to generate code for multiple processors but supported only communications by message passing. Since, in a multicore architecture, the cores communicates by shared memory, SynDEx was not able to generate code for multicore architecture. Consequently, this work consisted to add SHM communication features to SynDEx: SHM medium type SHM communication synchronization mechanisms Add a shared memory SynDEx executive kernel for code generation

T4: RTX multi-core code generation with SynDEx (INRIA) To make SynDEx being able to generate code for a new operating system, a SynDEx executive kernel dedicated to this OS must be developed. This work has been done in two steps: Adding a SynDEx executive kernel for Windows Adding a SynDEx executive kernel for RTX, based on the previous one, since RTX uses some parts of the Windows API

T5: xMOD multi-core code generation with SynDEx (INRIA/IFPEN) Based on the RTX SynDEx executive kernel, this kernel aims at modifying the software architecture to match the xMOD interface. Main difficulties was to keep the possibility for xMOD to access the models I/O, parameters and signals, while thread management, scheduling and distribution was totally delegated to SynDEx: For SynDEx: implement the xMOD interface in the generated code to be able to receive from xMOD the init, start and stop command, and the periodic timer For xMOD: modification to detect, command and trig SynDEx driven (schedule and distribution) real-time co-simulation. IFPEN and INRIA worked together, exchanging header descriptions to obtain a totally automatized tool chain and maximize the gain obtained by the two tools synergy.

T6: Automatic transformation of Simulink Superblock graph to a SynDEx algorithm and code generation for each Superblock (IFPEN) Consists in a new target for Real-time-Workshop. This target aims at analyzing a Simulink model and generate the following files: One executable library file per first level superblock of the initial graph: the powerful uniprocessor code generation of RTW is locally used, producing efficient sequential code. One model description file per superblock of the initial graph A SynDEx algorithm description (.sdx) corresponding to the high level Simulink graph Application specific code (.m4x): for each bloc of the SynDEx algorithm graph, this file specifies the code which has to be executed. Precisely, this is this file which describes the relation between the SynDEx blocks and the set of executable library.