INTRODUCTION TO MULTISCALAR ARCHITECTURE

When and how ? Multiscalar Architecture was a concept developed by Manoj Franklin. He was a student of the Computer Science dept in the university of Wisconsin-- Madison. He wrote a thesis on the subject for his doctorate in 1993.

What is multiscalar architecture ? The Multiscalar architecture uses a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential programs without improvements in clock speeds.

But how is it any better than Scalar or superscalar architectures ?

Scalar Processors Instruction Queue Execution Unit addu $20, $20, 16 ld $23, SYMVAL -16($20) move $17, $21 beq $SKIPINNER17, $0, ld $8, LELE($17) 5

SuperScalar Processors Instruction Queue Execution Unit addu $20, $20, 16 ld $23, SYMVAL -16($20) move $17, $21 beq $17, $0, SKIPINNER ld $8, LELE($17)

Multiscalar Architecture 7

Multiscalar Architecture Sequencer Queue of processing units Unidirectional ring. Each has an instruction cache, processing element, register file. Interconnect Data Bank Each has address resolution buffer, data cache.

Modern microprocessors achieve high performance by exploiting instruction level parallelism (ILP) in sequential programs. They establish a large dynamic window of instructions and employ wide-issue organizations to extract ILP and execute multiple instructions simultaneously. Larger windows enable more dynamic instructions to be examined, which leads to the identification of more independent instructions that can be executed by wider processors. However, large centralized hardware structures for larger windows and wider processors may be harder to engineer at high clock speeds due to quadratic wire delays, limiting overall performance.

Point 1 WINDOW 1 Point 2 WINDOW 2 Point 3 WINDOW 3 Point 4 A1 A2 A3 Task A B1 B2 B3 Task B C1 C2 C3 Task C

Multiscalar Programs Code for the tasks Small changes to existing ISA add specification of tasks no major overhaul Structure of the CFG and tasks Communications between tasks

So what is multiscalar processing ? The idea here is to connect multiple sequential processors in a decoupled and decentralized manner to achieve overall multiple issue. So it can be compared to multiple superscalar processors performing simultaneously. The fundamental performance issues are control flow speculation, data communication, data dependence speculation, load imbalance, and task overhead.

Continuation . . . In a Multiscalar processor, sequential programs are partitioned into sequential tasks. Task A Task B Task C PU PU PU Memory Disambiguation Unit (ARB)

Continuation . . . The above Figure shows a static program partitioned into three tasks and three points of search in the dynamic stream with three corresponding windows. Execution proceeds by assigning tasks to PUs(Processing Units). After assigning a task for execution, one of the possible successors of the task is predicted to be the next task. This is similar to branch prediction employed by superscalar machines, i.e., control flow speculation is used.

Address Resolution Buffer(ARB) ARB plays a key role in multiscalar processing. The basic idea behind the ARB is to allow out-of-order issue and execution of memory references. It also provide a hardware platform to order the references sequentially.

Thank You! References used for this presentation are The original thesis of Dr.Manoj Franklin. IEEE journal entry “Task Selection for a Multiscalar Processor” by T.N Vijaykumar,School of Electrical and Computer Engineering Purdue University and Gurindar S. Sohi ,Computer Sciences Department University of Wisconsin-Madison. The presentation “Multiscalar processors” by Matthew Misler,Gurindar S. Sohi, Scott E. Breach, T. N. Vijayjumar University of Wisconsin-Madison.