Presented by Richard Prentice Prepared by Richard Prentice Understanding and Comparisons of High Speed ADC and DAC Architectures TIPL 4706 Hello, and welcome to the TI Precision Lab discussing architectures of high speed ADC devices. First we will discuss the basic architecture of a flash ADC stage, and then show how that basic stage is used as the core structure in more complex ADC architectures such as a pipelined ADC. Interleaved ADCs are discussed as well as Successive Approximation ADCs. Finally the basic DAC core architecture is presented. Presented by Richard Prentice Prepared by Richard Prentice

Architectures Comparators Flash converter For n bits: Track and hold The most basic components of an A to D converter is the track and hold stage (also called sample and hold) followed by a flash converter stage. The track and hold stage at its most basic consists of a switch controlled by the sample clock and a sampling capacitor to hold the value to be digitized. During the portion of the sample clock when the clock is logic low the switch is closed, allowing the incoming analog signal to be present on the sampling cap. The voltage on the cap will ‘track’ the incoming signal during the clock low portion. Then when the sample clock transitions to a logic high the switch will open. This isolates the sampling cap from the incoming analog signal so that the cap ‘holds’ the voltage at the instant that the switch is opened. Thus the name ‘track and hold’ circuit. While the incoming signal has been ‘frozen’ on the sampling cap, the digitizer stage has half a clock period to transform the capacitor voltage to a digital code before the switch closes again and the device enters the track stage again. This illustration shows a simple 3-bit flash conversion stage. To digitize the signal to a 3-bit code would require 2^n – 1 voltage comparators, or 7 comparators. The voltage comparators are arranged with a series of threshold voltages, with the voltage to be converted being input to each of the comparators. If the analog input is higher than the lowest threshold voltage then that comparator output is active. If the voltage is higher than the second threshold voltage, then that comparator is active. If the voltage is higher than the third threshold then that comparator is active, and so on. After the 7 comparators there will be a set of 7 results of the comparators, often called a thermometer code. (This is because as the input voltage rises and falls the number of outputs active rises and falls somewhat like a thermometer.) At this point the thermometer code is a digital representation of the input signal, but it is more common to have some digital logic to convert the thermometer code into an arithmetic code. Finally, there remains the task of latching the arithmetic code into a register on the falling edge of the sample clock to catch the sample before the signal ‘held’ on the cap begins to change again. Comparators For n bits: 2n – 1 comparators

Architectures Pipelined – successive stages of flash Each stage adds n bits more precision Requires good matching/trimming A flash converter stage requires 2^n – 1 voltage comparators, which is reasonable for data converters of resolution of 5 or 6 bits. A 6 bit flash ADC would require 63 voltage comparators. This concept would not be practical for extensions to 12 or 14 bit ADCs. A 14 bit flash ADC would require 16535 voltage comparators! Even if this were reasonable to implement on a chip the difference between adjacent threshold voltages could be smaller than inherent offset error voltage of the comparators, causing poor linearity or even missing output codes. If a flash ADC converter stage is limited to 5 or 6 bits, then a higher precision data converter could be implemented in pipeline stages. A 14bit ADC implemented in three pipeline stages is illustrated here. The first ADC stage is a 5 bit flash stage, yielding a 5-bit resolution of the sample. But when this 5-bit sample is latched, the 5-bit code is converted back to an analog voltage by a matching internal 5-bit DAC. At this point we have the actual input voltage with its 5-bit code that represents that voltage and an ideal voltage that corresponds to the 5-bit code. The difference between the actual input voltage and the ‘ideal’ voltage assigned to that code is called the ‘residue’, or the quantization error between the actual voltage and the ideal voltage. But if we multiply this residue by a factor of 32 after a 5-bit flash ADC stage, then the residue is expanded out to the original full scale range of the ADC. Then this residue can be further quantized by a second flash ADC stage to gain more precision in the resulting sample. This cascade of pipeline stages could in theory be extended forever to gain unlimited resolution of the sample, but in practice small mismatches in gain between the different ADC stages, DAC stages, and residue amplifiers will lead to a build-up of error. Three or four pipeline stages are commonly feasible, depending on the accuracy of trimming the tolerances of all the individual components. Finally, there is commonly one bit of ‘overlap’ designed into the pipeline stages so that a slight mismatch between an ADC stage and its following DAC doesn’t lead to a ‘jump’ in the output code that might be larger than one least significant bit of the final code. This bit of overlap is resolved with arithmetic logic as the pieces from the individual stages are combined into a complete sample. In the example above, the first stage provides 5 bits of resolution, while the second stage provides an additional 4 bits of resolution, and the final stage provides an additional 5 bits of resolution for a final sample of 14 bits.

Architectures SAR – Successive Approximation DAC = digital-to-analog converter EOC = end of conversion SAR = successive approximation register S/H = sample and hold circuit Vin = input voltage Vref = reference voltage Source - Wikipedia Another approach to higher resolution conversion is the Successive Approximation ADC. In this architecture, the analog input signal is also ‘frozen’ in a sample and hold or track and hold circuit as was used in the flash or pipelined ADC. But after the input signal is being held by the track and hold circuit the method of converting this voltage to a digital code is different. In this approach, the ADC iteratively adds a bit of resolution per iteration until the desired number of bits have been derived. A single comparator is used, but with a DAC stage to iteratively generate a succession of threshold voltages. The first threshold voltage determines the most significant bit of the sample comparing if the input voltage is above or below midscale. If it is above midscale the MSB is 1 and the DAC moves on to the next threshold voltage which would be halfway between mid-scale and full-scale. After the desired number of bits have been derived, the sample is output with a signal for End Of Conversion. One disadvantage of this approach is that the maximum conversion rate is limited by the speed of the DAC plus comparator, divided by the number of bit iterations that must be performed. Thus this architecture is most often used for relatively low speed and low power but higher resolution ADCs. (commonly 16 or 18 bits or even more)

ADC Interleaving Basics Multiple ADC cores sample signal to increase total sampling rate ADC cores sample at same divided frequency but different phase offset Digital outputs are re-aligned in time Input buffer typically drives cores For a single pipelined ADC the maximum sample rate will be largely limited by the time for the flash ADC stage to settle and get its output latched in half a clock cycle. One common way to achieve higher sample rates is to use multiple ADCs in parallel with the clocking delayed and staggered. Benefits are a much higher achievable sample rate than can be achieved in a single ADC for a given process node. Drawbacks include the requirement to distribute the input signal to all interleaved ADCs without skew or amplitude mismatches, and increased loading and distribution burdens on the analog input signal and the clock distribution. Mismatches in clocking or analog signal distribution will lead to distortions in the sampled data and loss of performance. 5

Non-Ideal Interleaving Offset Errors Mismatched ADC core voltage offset Amplitude Errors ADC core gain error ADC reference voltage error Phase Errors Input routing delay Input BW difference Clock phase error ADC sampling instant ADC1 ADC2 BUFFER Signal Input 0º 180º Clock Phase Generator Clock Input freq. = Fs freq. = Fs/2 GERR VOFFSET ERR Common sources of errors in interleaved ADCs include offset mismatch, amplitude mismatch, and clock phase mismatch. Offset mismatch and gain mismatch are relatively easy to correct for by way of digital logic operating on the sample data stream following the sub-ADCs. Digital logic could be designed to generate an estimate of offset mismatch and/or gain mismatch from the sample data from each sub-ADC. Then the estimated offset error could be subtracted from the sample data in real time with arithmetic logic. Likewise the estimated gain error could be used to compensate the sample data in real time with multiplication logic. Phase error compensation is more difficult to correct in real time. 6

Non-Ideal Interleaving Offset Error Different voltage offset at ADC input between different cores Alternating up/down in transient waveform Creates signal independent spurs in spectrum at Fs*n/N for n=1,2,…,N-1 where N is # of interleaved cores Example N=2 Offset error is due to different DC offset voltages for the different interleaved ADC cores in a design. In this example the red waveform is the waveform as seen by one interleaved ADC while the green waveform is the waveform as seen by the other interleaved ADC. For uncorrected offset error, the result of the error has the appearance of a sawtooth pattern on top of the ideal sample pattern with samples alternately higher or lower in value than ideal. In the frequency domain this tends to look like spurs in the resulting FFT spectrum at the Nyquist (Fs/2) rate for 2-way interleaving or multiples of Fs/4 for 4-way interleaving. Input Signal Offset spurs Power Freq FIN FS/4 FS/2 Example N=4 7

Non-Ideal Interleaving Amplitude (Gain) errors Gain difference between different ADC cores Creates N-1 input signal dependent images from 0 to Fs/2 in a repetitive, mirror-image pattern where N is # of interleaved cores Also creates harmonic distortion images Gain error is due to different gain values for the different interleaved ADC cores in a design. In this example the red waveform is the waveform as seen by one interleaved ADC while the green waveform is the waveform as seen by the other interleaved ADC. Uncorrected gain error also gives rise to a sawtooth appearance on the sample data as was the case with offset error, but with the difference that the direction of the error inverts as it crosses mid-scale. In the above example where the red waveform is reduced in gain, above midscale the sample is lower than the ideal code and below midscale the sample is higher than the ideal code. The resulting spectrum is more complicated that that of simple offset error, with repeating images dependent on the frequency of the input signal. In the sketch of spectrum shown the repeating images of the input signal is shown as well as repeating images of the 2nd harmonic of the input signal. Input Signal Input Images H2 Images Power H2 Freq FIN FS/4 FS/2 Example N=4 8

Interleaving Correction Relying on process matching not suitable for most applications Interleave correction reduces spectrum offset spurs and images Estimate the errors and correct the data with coefficients Estimation Detection in time-domain or frequency domain Convergence Correction Analog/Digital Calibration time Foreground: Calibration interrupts normal operation Background: Calibration runs continuously There are a range of options for how to deal with mismatches in interleaved systems. For applications requiring higher sample rate with less emphasis on performance, interleaving that relies of matching of external factors such as length of signal routing to the ADCs might be adequate. To maintain AC performance in terms of signal to noise ratio or harmonic performance it may be necessary to perform some kind of interleaving correction. This generally involves some method to estimate the magnitude of the mismatch, and then some manner of correcting for the mismatch. The correction could be applied to the analog signal prior to the sampling, or applied digitally to the sample data after conversion. The estimation function could be performed at one time initially, in which case the estimate would not account for drifting of environmental conditions such as temperature unless a recalibration were to be performed at certain intervals. The estimation function may be performed continuously on a sliding window of sample data during normal operation of the ADC. One drawback of most estimation algorithms used to estimate gain or offset mismatch is the possibility of a pathological input pattern that performs poorly for the estimation algorithm employed. 9

= Current Steering DAC DAC Full Scale = 30mA Decoder Logic Digital Input Data Switch Drivers Current Source Array Bias Circuit IOUT1 Switch Array IOUT2 Analog Output DAC = 30mA 0mA 15mA IOUT2 IOUT1 Full Scale = 30mA Digital to Analog Conversion is not simply the opposite of Analog to Digital Conversion. The simplest architecture for a DAC is the Current Steering circuit. The DAC is designed to move a certain amount of current into or out of a ‘Load’, and ohms law relates this current to the output voltage. In this example, if the Full Scale output of a DAC is 30mA into a 50 ohm load, then the full scale output voltage would be 1.5V single ended (or 3.0V peak to peak differential in the above example).

DACs can be current source or current sink PMOS NMOS VCC+ 0.5 Volts +1/0.5 Volts - 1/0.5 Volts Iout Ioutb VCC Ioutb Iout VCC - 0.5 Volts Current Source Cascodes Switches Current steering DACs could be of the current sink or the current source type. The difference is in whether the DAC current source is from the DAC supply through the load resistor to ground, or from the external pull-up supply through the load resistor and then sinking to ground through the DAC. A current source DAC would typically be designed with P-channel devices for the current source while a current sink DAC would typically be designed with N-channel transistors. In either case, the output voltage would be determined by ohms law considering the amount of current though the load resistor. Switches Current Sink Cascodes DAC5686/87/88/89, DAC5681/82Z, DAC3282/83 DAC3152/62 DAC90x, DAC290x, DAC2932, DAC56x2 DAC34xx, DAC3174

Simple 3-bit Binary DAC AVDD AVDD Pro: Least number of current sources and switches. Con: Higher distortion. 1000 1000 Vout 1 1 1 bit 3 bit 2 bit 1 500uA 250uA 125uA (875u*1K) Whether current source or current sink, one approach would be to implement the DAC output stage as a parallel combination of current-mode drivers, with the current capabiltity of each driver scaled by a power of two compared to the adjacent drivers. In this simple 3-bit example, the driver for the most significant bit has a current capacity of 500 microamps, while the next bit has a capacity of 250 microamps and 125 microamps for the least significant bit. The full scale output would be with all three drivers active for a current of +/- 875 uV. The advantage of this approach is that for a resolution of N bits only N output drivers need to be designed to output in parallel. The disadvantage is that matching the output drivers is difficult to achieve for larger bit counts, as the tolerance of the msb could possibly swamp that of the resolution intended for the lsb. Unless the tolerance of the proper power of 2 scaling from the msb down to the lsb is held, the linearity of the DAC would suffer. (625u*1K) (375u*1K) (125u*1K) Vout – (125u*1K) – (375u*1K) – (625u*1K) – (875u*1K) bit1 and bit2 turn off, bit3 turns on 000 001 010 011 100 101 110 111 bit 3 bit 2 bit 1

Equivalent 3-bit Thermometer Coded DAC AVDD AVDD Pro: Reduced distortion (easier to match equal current sources.) Con: More current sources and switches required. 1000 1000 Vout 1 1 1 therm 7 therm 2 therm 1 125uA 125uA 125uA Another approach to the DAC current output is to make the output drivers matched in current capacity. In this approach it is easier to hold the tolerances of the output drivers to achieve good matching from one driver to the next, but there now would need to be 2^N – 1 output drivers for N bits of resolution. The example 3bit DAC shown would require 7 output drivers of equal current capacity. Full scale output would require all drivers be active in parallel. In this case the input sample code would be converted from an arithmetic code to a thermometer code, and each bit of the thermometer code would control an individual output driver. Better matching can be achieved across the output drivers in this structure, but for higher resolution samples the number of drivers to implement becomes prohibitive. A 14 bit DAC would require 16535 output drivers in parallel. (875u*1K) (625u*1K) (375u*1K) (125u*1K) Vout – (125u*1K) – (375u*1K) – (625u*1K) – (875u*1K) one more equal valued current source turns on 0000000 0000001 0000011 0000111 0001111 0011111 0111111 1111111 bit 3 bit 2 bit 1

DACs can be segmented and mixed coded therm(7:1) to MSB segment AVDD AVDD input 6b word decoder logic bit(3:1) to LSB segment 1000 1000 Vout 1 1 1 therm 7 therm 2 therm 1 Thermometer 3b MSB DAC 125uA 125uA 125uA To achieve a higher resolution DAC a combination of the binary DAC and thermometer coded DAC may be employed. In this example, a 6 bit DAC may use the upper three bits of the sample to control a thermometer coded DAC, so that there need only be 7 matched current drivers in parallel. Then the lower three bits may be used to control three more current drivers that are scaled by powers of 2 in size. In this way the matching of the current scaling only has to span 2 to the power of 4. Higher resolution DACs such as 14 to 16 bits would likely be implemented by this mix of coding styles. 1 1 1 bit 3 bit 2 bit 1 Binary 3b LSB DAC 62.5uA 31.25uA 15.625uA

Simplified TI 16b DAC topology Ex: DAC34xx IOUT1 IOUT2 MSB Thermo(63:0) MSB segment decoding D(15:10) (6 MSB Bits) 73 switches 73 switch drivers LSB binary(9:0) LSB segment decoding D(9:0) (10 LSB Bits) For a 16 bit DAC example, the upper 6 bits of the sample are converted into a 63 bit thermometer code to drive 63 matched current sources. At the same time the lower 10 bits of the sample are used directly to drive 10 scaled current sources – also in parallel with the 63 matched current sources. Thus the total number of current drivers is 73, and the matching of the scaled binary current drivers must be matched well across a span of 2 to the power of 11. (The 10 binary drivers are scaled across a span of 2 to the power of 10, but the thermometer coded drivers are all 2 times the size of the largest of the scaled drivers.) 63 10 MSB cascodes LSB cascodes EXTIO bias circuits MSB current sources LSB current sources RBIAS

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