Purdue Microbrewer: A Microcontroller Generator Jacob R. Stevens, John Skubic, Eric Colter, Dr. Matthew Swabey, Dr. Mark Johnson

Purdue Microbrewer Custom microcontroller generator Goals: be able to… Generates HDL and FPGA synthesis script from library of IP Generates documentation and drivers, aiding adoption Goals: be able to… quickly create a custom microcontroller flash it to an FPGA support board use that board just like a commodity microcontroller board Allows: Schools to design custom educational platforms Makers to have application specific microcontrollers Researchers access to an easy to use test platform

Current Solutions Custom RISCV Silicon Solutions Commodity Microcontroller Custom RISCV Silicon Solutions Inexpensive Rich open source ecosystem Accessible (Arduino, Energia, etc) Not application specific Potentially royalty free Uses an open ISA High barrier to entry Can be tailored to application

Commodity Microcontroller Purdue Microbrewer Commodity Microcontroller Custom RISCV Silicon Extremely customizable Usage feels like commodity microcontrollers Low barrier to entry

A Motivating Example: Addressable LEDs The popular WS2812 (NeoPixel) LEDs use a timing-critical unipolar communication protocol No mainstream microcontroller offers hard IP for protocol Without Purdue Microbrewer: Must use assembly and knowledge of frequency of microcontroller in order to communicate Core cannot be interrupted during communication Library must be adapted based on ISA and operating frequency With Purdue Microbrewer: Design the peripheral once, applicable for any end user! Communication can be offloaded, freeing up core

Architecture Microbrewer Developer Microbrewer Tool Microbrewer Output Microbrewer User External EDA Tools

Microbrewer Configuration File Microbrewer user specifies: Peripherals used Bus topology Bus endianness Names of chip and peripheral instances Microbrewer runs sanity checks on configuration file Fit number of IO pads of supported FPGA? Fit inside supported memory map?

Core Uses RISCV Business core as described by John Allows user to customize not only bus topology and included peripherals, but also ISA extensions and microarchitectural configurations Any RISCV core that uses a standard bus interface can be used as well

Peripherals Examples of developed peripherals: UART, PWM, GPIO, SPI Community can contribute peripherals XML is used to describe the peripheral and generate documentation/drivers Includes information such as: Peripheral name Address space needed IO pins needed Register and field definitions

Driver & Documentation Automatically generates drivers & documentation based on peripheral’s XML file Standardizes layout of documentation, important for consistency across open source project contributions Multiple options such as Wiki markup Easy to add new formats such as Latex, Markdown, etc Driver generation aims to minimize need for low level code, simplify process of writing libraries for peripherals

Example Peripheral XML File

Example Drivers

Example Documentation

FPGA Target Board Will provide a supported FPGA board Allows for users to get started without board design experience Allows for FPGA board to be more similar to a commodity microcontroller board than usual FPGA boards Must be easy for other FPGA boards to be targeted Regardless of vendor

Current Progress As shown, majority of progress is on the peripheral level IP development, XML definition, driver & documentation generator Standard FPGA board currently being designed Important next steps: Sanity check script for Microbrewer XML configuration file Automatic generation of bus interconnect and top level instantiations/defines Automatic pin mapping to FPGA

Acknowledgements We wish to acknowledge current and recent SoCet team members who have contributed to the design, verification, and testing of modules or software that were the precursors to Purdue MicroBrewer: Yunus Akhtar, Andrew Brito, David Castley, Gregory Chang, Noah Chesnut, Allen Chien, Yuchen Cui, Dwezil D'souza, Siddhant Ekale, Haoyue Gao, Travis Garza, Mingxuan He, Yaqin Huang, Jiangshan Jing, Ruchit Kank, Prashant Lalwani, Annan Ma, Arnav Mittal, Chandan , Muddamsetty, Trevor Odelberg, Erin Rasmussen, Sudharson Ravishankar, Kevin Rockwell, Manik Singhal, Sam Sowell, Erik Swan, Chuan Yean Tan, Xin Tze (Joyce) Tee, Todd Wild (ECE Industry Design Projects Manager), Kyle Woodworth, and Aliasger Zaidy.

Questions?

Speaker Bio Jacob R. Stevens is a Ross Fellow researching in the Integrated Systems Lab at Purdue University under Dr. Anand Raghunathan. He graduated in 2016 from Purdue University with a Bachelor’s degree in Computer Engineering and continued on to pursue his PhD in SoC architecture. He has interned in the past for Qualcomm, in both software and hardware engineering roles. He has also been a member of the Purdue SoCET team since 2013. His research interests include accelerator-based computing and EDA.