Valérie Chambert and Joël Pouthas Summary of the March 29th/30th Orsay Meeting on PANDA EMC Barrel electronics Valérie Chambert and Joël Pouthas I.P.N. Orsay, France

EMC Barrel 11 360 crystals 16 slices 710 crystals per slice in Philippe Rosier Valérie Chambert, Joël Pouthas, April 14th-16th 2010, PANDA Workshop, Gießen

EMC electronics general schematic DATA Multiplexer CSA/Shaper Digitizer module DAQ SODA Optical Links 100 MB/s 30 Data multiplexers Igor Konorov Valérie Chambert, Joël Pouthas, April 14th-16th 2010, PANDA workshop, Gießen

Electronics requirements 11360 crystals, 2APD/crystals 22720 electronics channels Dynamic range : 10000 (13/14bits) Rate : max 150kHz per crystal@107 interaction rate Power consumption compatible with cooling and temperature stability specially for the -25°C zone Radiation hardness ? Valérie Chambert, Joël Pouthas, April 14th-16th 2010, PANDA workshop, Gießen

FE electronics for 4 crystals 4 crystals in 1 alveole 4 APFEL ASIC (Dual channels, 2 gains/channel) ADC ADC M U L T I P E X R SODA FPGA DATA 1.52Gbit N= ? 8 APDs N x16 ADCs DIGITIZER PREPROCESSING -25°C Room temperature Valérie Chambert, Joël Pouthas, April 14th-16th 2010, PANDA workshop, Gießen

FE electronics integration Philippe Rosier Valérie Chambert, Joël Pouthas, April 14th-16th 2010, PANDA workshop, Gießen

FE electronics integration (Present status) -25°C Flex connection APFEL (ASIC Chip ) ASIC Board 19.5x19.5 mm2 Philippe Rosier M. Kavatsyuk , P. Rosier Valérie Chambert, Joël Pouthas, April 14th-16th 2010, PANDA workshop, Gießen

APFEL Circuit (GSI) Electronics measurements of the 2009 version [2 ranges (1, 32)] within specs Dynamic range 10000 Change of the high gain from 32 to 16 for better resolution up to 600 MeV better overlap with the low gain Power consumption 100mW/crystal Compatible with cooling ? To be tested 200 chips foreseen in 2010 Characterization with crystals and digital electronics must be done with test beam DAC Vref1 DAC Vref2 Band Gap DAC control (to be implemented) H. Flemming , P.Wieczorek Valérie Chambert, Joël Pouthas, April 14th-16th 2010, PANDA workshop, Gießen

Sub-ranges E ADC 300keV/ch 600keV/ch 10MeV/ch 1024 G=1 G=32 G=16 64 32 10GeV Valérie Chambert, Joël Pouthas, April 14th-16th 2010, PANDA workshop, Gießen

Digitizer Preprocessing Digitizer functionality: Digitization Zero suppression Feature extraction: time & amplitude Time ordering and data formatting Integrated slow control : T,V, I Fast serial optical link to Multiplexer Igor Konorov In 2010 Uppsala prototype 16x14bits/100Mhz ADC with 1 FPGA Add APFEL DAC control into the FPGA To be continued : Number of ADC per FPGA (16 ? 32 ?..) DATA formating and transfert (KVI) Calculation algorithms for time and amplitude (KVI) Pile up management (KVI)

Prototypes Existing: In progress : Proto60 : Preamp Basel+KVI shaping+ADC) In progress : Proto Uppsala 16 ADC+1 FPGA To be done : test beam Crystal+ APFEL+ digitizer

Some numbers EMC is 11360 crystals 22720 APD 11360 FE chips + PCB (to be produced and tested) 2 or 3 FE industrial tests benches 45440 ADC on 2840 or 1420 digitizer preprocessing modules 30 (?) data multiplexers (concentrators ?) at least 2840 FPGA for the DATA processing …A Huge project

Conclusions Digitization and local DATA processing is presently considered (counting rate & dynamic range issues) Electronics integration must be carefully studied Electronics power consumption must be checked Cost will be an important parameter Notes Hit detection ASIC design to reduce the ADC number (studied by GSI) Identification of clusters by the electronics : problem of slices boundaries (concentrators ?)