Analog and digital signal processing in the liquid argon calorimeter trigger system of ATLAS detector in the High-Luminosity LHC PACHECO RODRIGUEZ Laura Thesis project for IRFU/SPP & IRFU/SEDI Advisors: SCHWEMLING Philippe, DESCHAMPS Hervé Electronics Engineer degree Master in Photonics Instrumentation PhD  R&D in Particle Physics Applied research for physics sciences

Outline Introduction My thesis work Results LHC ATLAS LAr Calorimeter upgrade My thesis work Digitizer board development Demonstrator Data Studies Results

Large Hadron Collider (LHC) Goal is to test the predictions of different theories in high-energy physics: about evolution of the universe, matter constituents… Built by the European Organization for Nuclear Research (CERN) First operation in 2008 Proton-proton & Pb-Pb collisions at 40MHz Center of mass energy 14 TeV Luminosity: L = 1034 cm−2s−1

ATLAS ATLAS trigger (L1) Calorimeter. Energy Threshold ET General detector: investigate Higgs boson (identified in 2012), CP violation, provide EW symmetry breaking details, search of extra dimensions, look for new physics… Sub-detectors Inner detector. Tracker of all charged particles Calorimeter. Energy measurement Muon Spectrometer. Muon Tracker ATLAS trigger (L1) Calorimeter. Energy Threshold ET Muon spectrometer. Momentum threshold pT Liquid Argon (LAr) Calorimeter. Liquid argon as active medium. Measure the E deposited by electrons & photons.

LAr Calorimeter Upgrade HL-LHC (2026) Luminosity increases 5 times Trigger rates dominated by background (QCD jets) producing fake triggers. QCD jets distinguishable from EM particles if looking at shower shape. GOAL: Keep present trigger rates by improving selectivity of trigger Finer segmentation x10 BEFORE AFTER UPGRADE

LAr Calorimeter Upgrade Demonstrator System LAr trigger readout architecture Installation in summer 2014 Currently taking data Co-design of CEA Saclay & LAL (Laboratoire de l'Accélérateur Linéaire)

My thesis work Digitizer board development Analysis of data from Demonstrator My thesis work

Digitizer board development Test bench For assessment of LTDB Analog part. Digitization of LAr-like pulses, optical transmission. Stability Linearity Frequency domain response Noise (Cross talk…) Amplification stages … Block diagram of Digitizer board

Implemetation of low jitter clock system. Digitizer board development A/D conversion Sampling 32 channels at 40MHz (Frequency of collisions) Scale digitization in the order of calorimeter noise (32MeV & 125MeV depending of the region on calorimeter) ADC range (for ET values up to 102 GeV and 400 GeV) ADC characteristiques: LTM9007  ADC Demo board (DC1751) 2Vpp Analog inputs 14-bit, 8-channels, 40Mbps Serial interface LSB=122µV Implemetation of low jitter clock system. CLK Cleaner: 300fs jitter Buffer: 0.25ps jitter ΔV<30µV Aperture error less than 1LSB (122µV) if jitter<3ps LAr-like pulses sampled by ADC

Digitizer board development Serialization & optical transmission 8-ch ADC Serial Serial Transmission FPGA Artix-7 (XC7A200T) SER/DES, FIFO memories (deep of 256 words), 4 transceivers Encoding 8b/10b, 1 Ctrl word / 65 words = 6.5Gbps Memories & data format Parallel Good CLK sync trans/receiver Comma symbol every 1.6µs FPGA Firmware Simulated. ModelSim  Timing constraints validated Implemented in FPGA Evaluation Kit. Optical communication tests FPGA(Artix7)<->FPGA(Virtex5) Eye diagram of optical tranmission

Digitizer board development Power system 2 Rails 2.5V (Imax=3A) & 3.3V (Imax=3A) = 17.4Wmax 9 voltage sources(1V, 1.2V, 1.8V, 2.5V) Power up sequence (~1.5s for timing ON) for prevent excessive current draw during startup. Some stages simulated & validated in LTSpice Time to ON & Power sequencing ΔV ripple (order of nV in steady state) Power Calculations: Board power consumption (No FPGA) <9W FPGA. Xilinx Power Estimator. Total On-chip power ~ 0.624W Next steps Implementing Board Electronic schematic OK PCB routing started PCB cablling to be done Test & verification to be done Test bench setup to be done LTDB evaluation to be done

Demonstrator Data Analysis Goals: Debugging & assessment of Demonstrator (FE & BE electronics) Study demonstrator electronics performances DATA TAKEN: Calibration runs Physics runs during Run 2 (2015, 2016) PP runs ~1.8 M events HI runs ~360 K events. BE Firmware Version Used in ATLAS since 0.94 0.94c 27.10.2015 0.94d 24.11.2015 0.94e 26.11.2015 0.94f* - 0.94g 1.12.2015 0.95a 31.03.2016 0.95b 11.04.2016 0.96 11.05.2016 0.96b 21.06.2016 0.96b1 28.06.2016 0.96c 30.06.2016 Data Studies Detection of data taking problems (channel connectivity, errors in transmission, readout issues)  Useful information for firmware development

During HI (bleu) & PP (green) collisions Demonstrator Data Analysis Data Studies Analysis of pedestal. Luminosity correlation effects. Pedestal Useful for energy reconstruction and calibration (pedestal subtraction) Polluted by electronics and pileup noise. As the luminosity increases, pileup becomes the dominant contribution to the total noise. Thank to upgrade is possible to measure the pedestal event-by-event during collisions (pileup effects). eta<=0.4, layer=1 Pedestal RMS During HI (bleu) & PP (green) collisions

Results Digitizer Board was designed and some stages were successfully tested by simuation and implementation. PCB routing has started. Data taking studies have allowed the commissioning of Demonstrator System (still ongoing) and the confirmation of luminosity influence in Pedestal RMS To do… We expect the digitizer board will be ready in next months to start testing LTDB performances. Pulse timing studies to be performed.

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FPGA CONFIGURATION

LAr calorimeter segmentation for upgrade Resolution increased 10 times: Longitudinal segmentation in 4 layers (PS, Front, Middle, Back) Finer resolution in n and φ region for 2 & 3 layers. Quantization scale High precision (level of noise) 125 MeV in the middle layer and 32 MeV elsewhere. (compared to 1GeV for Run2)

Trigger system Instantaneous Luminosity increases:  increase number of interactions per bunch crossing (µ): 40 [Run 1] —> 50 [Run 2] —> 80 [Run 3] increase occupancy (more fakes (non-physics) trigger) EM Calorimeter triggers:  Selection of EM objets (photons, electrons, T leptons) Expected to increase linearly with L. L1 trigger rate is limited to 100kHz!!

Qualification task Most frequently presented issues: 1 year stay in CERN Work on LAr Operations Team : Group of experts controling the operation of LAr sub-detector Tasks: Monitoring of LAr HW ressources/infrastructure Watch out for LAr alarms React to problems quickly (data quality is in play!) by fixing the issue or by investigating and reporting to concerned people. Control HW ressources. Report issues everyday. LAr DCS (Detector & Control System) Most frequently presented issues: HV Trips in power supplies for LAr electrodes Problems in monitoring readout (bit flips, bus communication,…). Shorts circuits in LAr electrodes DCS system is a tool allowing the interface (monitoring & ctrl) to the detector.