SVD FADC SVD-PXD Göttingen, 25 September 2012 Markus Friedl (HEPHY Vienna)

Introduction Front-End Junction Box FADC Summary M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Introduction Front-End Junction Box FADC Summary M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Readout Chain Overview Analog APV25 readout is through copper cable to FADCs Junction box provides LV to front-end 1748 APV25 chips Front-end hybrids Rad-hard DC/DC converters Analog level translation, data sparsification and hit time reconstruction Unified Belle II DAQ system ~2m copper cable Junction box ~10m copper cable FADC Unified optical data link (>20m) Finesse Transmitter Board (FTB) COPPER M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Not Entirely New… 2007: plans for an intermediate upgrade of Belle I SVD Prototype system built and tested thoroughly in several beam tests since then Now enlarging and improving details, but concept is same See reports at previous TWEPPs for details & performance M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Introduction Front-End Junction Box FADC Summary M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

APV25 Readout Chip Schematics of one channel Developed for CMS (LHC) by IC London and RAL (70k chips installed) 0.25 µm CMOS process (>100 MRad tolerant) 40 MHz clock (adjustable), 128 channels 192 cell analog pipeline  no dead time 50 ns shaping time  low occupancy Noise: 250 e + 36 e/pF  must minimize capacitive load!!! Multi-peak mode (read out several samples along shaping curve) Thinning to 100µm successful M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Front-End Hybrids 2 variants Standard PCBs outside acceptance for the edge sensors “Origami” chip-on-sensor concept for inner sensors New idea: use Origami concept for all barrel sensors Decision to be taken at November B2GM M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Introduction Front-End Junction Box FADC Summary M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Junction Box: Mother Board Junction box board with CERN DC/DC converters to be placed in SVD DOCK boxes Converter boards now have a commercial chip, to be replaced by the rad-hard AMIS5 chip M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

DC/DC Converter: Noise Comparison Test hybrid (larger) Belle II design (smaller) Same noise within measurement precision (few %) between conventional and DC/DC powering! M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Junction Box: Draft Design (Top lid not shown) As in Belle 1 SVD: Located ~2m from front-end (outside acceptance) = radiation zone Mostly aluminum, only bottom plate copper (to be cooled) M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Introduction Front-End Junction Box FADC Summary M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Readout Electronics: Scheme No direct connection between power supplies and FADC Bias currents are measured remotely by FADC M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

FADC Block Diagram Analog & digital level translation between  bias and GND Digitization, signal conditioning (FIR filter), data processing Central FPGA is an Altera Stratix IV GX M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

FADC: Overall Concept Similar to Belle 1 SVD FADC, but with twice higher density (48 APV25 inputs) and more powerful FPGA M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

FADC: Level Translation Daughter Boards Analog board: existing design, but simplified Digital board: completely new design based on digital isolator ICs (Analog Devices) No floating LV power needed for either board! M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Analog Daughter Board 1 of 6 channels HV side GND side Essentially a differential high pass (time constant ~0.5 ms) Output levels optimized for AD9222 A/D converter (located on the main board) Protection diodes and 100 W series resistor drain stored energy in case of HV loss M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Digital Daughter Board GND side HV side M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

FADC: Level Translation Tests APV25 Hybrid Ana+Digi daughter boards on adapter board APVDAQ Repeater Both boards tested thoroughly, working perfectly fine  Short (2m) and long (12m) cable to FADC 100V between floating and GND sides No damage with repeated instantaneous shorting of HV M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

FADC: Central Intelligence Altera Stratix 4GX (EP4SGX180KF40C2N) 1517 pins (744 I/O) BGA 88 high-speed SERDES (48 needed for FADCs) Already purchased 3 devices (at 4k€ each) Found suitable high-speed connectors and now designing daughter board (then mother board) Basic firmware exists in present FADC prototype Will be converted and extended once hardware finished M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Other Devices on the FADC 8 x ADC Analog Devices AD9222ABCPZ-50 octal 50 MS/s, 12 bit digitizer with serial LVDS output 1 x Jitter cleaner Silicon Labs Si5317 2 x Phase adjustment CERN Delay25 4 differential channels, 0.5 ns step size 3 x Current monitoring Linear Technology LTC2499 Octal 24bit  ADC with I2C interface M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Introduction Front-End Junction Box FADC Summary M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Overall Readout System Scheme DAQ: PC Farm COPPER: common readout platform FADC system with optical link to COPPER DOCK box with DC/DC Front-End M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012

Summary & Outlook Readout Chain Based on a 2007 design (for an earlier update option)  Origami concept for all barrel sensors? To be decided at November B2GM Junction box near front-end with rad-hard DC/DC converters No noise penalty from switching power  FADC with powerful FPGA for online signal processing Level translation daughter boards – working fine  FADC design done on paper, now transferring to CAD for layout Starting with FPGA daughter board, then main board M.Friedl (HEPHY Vienna): SVD FADC 25 September 2012