Short report on status of hardware development at CNS 1 Short report on status of hardware development at CNS Taku Gunji Center for Nuclear Study University of Tokyo

Our detector design Simulation study is on going by Tomoya. 2 Our detector design Simulation study is on going by Tomoya. Almost ready for full simulation. Many issues (clustering/splitting/chi2 in lateral and longitudinal/pi0 efficiency by pad/strips) have been evaluated. Detector design 21 layers, 3 segments, 7 layers/segment 64 pads in lateral /segment Summing up raw signals between 7 layers. Independent readout for strips

Pi0 annual yield annual yield for pi0 measurement in p+p/p+A 3 Need to scale according to expected Integrated luminosity.  10^{30}x 10^{7} =10^{37}[cm^-2} =10^{41}{m-2} =10^{13}[b-1]=10pb-1 =10^{10}[mb-1] 10^{4} of pi0 @ pT=20GeV 10^{2} of pi0 @ pT=30GeV pT<40GeV is the maximum reach in annual year.  450 GeV in total E. Pi0 gamma from pi0 prompt photon Prompt photon in p+Pb/p+p 104

Requirement for pad readout 4 Requirement for pad readout Dynamic range: MIP – 500GeV Sampling fraction = 1% at 2nd segment for 500GeV dE=1.2MeV (MIP) – 5GeV Range in units of charge 50fc – 200pC Dual gain amplifier Assuming 12 bit FADC, +- 2.5V as maximum High: 50fc  10pC : LSB(E/ch) = 0.02GeV/ch Low: 1pC  200pC : LSB(E/ch) = 0.1GeV/ch

Dual gain preamplifier 5 Dual gain preamplifier Capacitive division (Chigh : Clow = 10:1) This works if preamp has large open loop gain. Saturation Protection circuit (high side) is implemented to avoid the change in impedance (this leads to cross-talks). S/N=10 @ MIP (50fC) High: S/N=10-2000 (use from 50fC to 10pC) Low: S/N=200-4000(use from 10pC to 200pC), dE/E=4% @ 10pC (S/N does not contribute to the resolution, 20/sqrt(E)>>noise/E) Pads P-Z Shaper (dual integrator) (+ Differential driver) Low High FADC Clow= 0.1*Chigh

First Prototype First dual preamplifier prototype by RIKEN Chigh 6 First Prototype Clow Chigh SA(high gain) SA(low gain) First dual preamplifier prototype by RIKEN Only high/low preamplifier part Noise FWHM~90keV (S/N>10@MIP) Linearity : 10000 0.15 MeV – 1.5GeV (need to enlarge up to 5GeV for our purpose)

hSPICE simulation and linearity 7 hSPICE simulation and linearity Include PZ and dual integrator (tpeak ~ 2usec) First version will be produced by TSMC 0.5um process. Linearity Good linearity up to 200pC 2.5usec

Another type of readout 8 Another type of readout Charge to time converter Pros: No digitizer. Just use FPGA (<1GHz) as TDC/TMC Not limited by the input range of ADC Reduce power consumption for signal driving Flexible for the range and adjustable according to rate Cons: Noise Primitive version to be made to see how feasible it is. Sample/hold + current source + CMOS switches Alternative QTC design is on going (integrator + current source without switches).

Block diagram and linearity 9 Block diagram and linearity Block diagram for prototype Two lines after the shaper : comparator + LVDS driver (for self trigger/start generation) QTC + comparator + LVDS driver 5pF as sampler, 2.5uA as current  range <2.5V/(2.5uA/5pF) = 5usec The current is adjustable to enlarge the range and resolution per bit high From shaper low To Comparator, LVDS driver

Plan Production of prototype 2 types of ASICs Another type of QTC is 10 Plan Production of prototype 2 types of ASICs TSMC 0.5um process: 4-8 channel/4mm2 Dual amp + shaper : layout wad done Dual amp + shaper + QTC : fine tuning of W/L for CMOS switches was done. Next is the layout. Available first versions of them around Feb. 2011. Another type of QTC is under developing. Production will start from April 2011. Vin = 0.1pC, 0.5pC, 1pC, 2pC, 5pC, 10pC, 20pC, 30pC

Readout plan Some basic information (per tower) 11 Readout plan Some basic information (per tower) One tower contains 64x3(segments) = 192channel 3 ASIC boards (64ch/board) 3 ADC/TDC & FPGA boards (128ch output/board) FEE: ADC /TDC & FPGA board (6U?) ( sitting in rack crate for the power) ASIC board (64ch/board128 ch out) Summing board (64 x 3) Scalable Readout Unit Fast analog/digital out for trigger? (This can be done via backplane…) Strips are not in this figure Hard to replace ASIC board? Cable driving (HDMI/Flat?) (length is not this scale!)

ADC/TDC & FPGA board At least, 10 bit is not enough. More than 12 bit. Commercial FADC (TI, AD,,,) with multi-channel/chip, 10-50MSPS, low power consumption Roughly speaking, data size in p+A could be: 0.3(occupancy) x 256 (tower) x 64 x 3 (ch/tower ) x 2 (H/L) x 12 (bit) x 20 (# of samples) = 0.9MB/event Reference: dN/dy=700, 15MB/evt (TPC), 1.1MB/evt (TRD) Need to extrapolate to A+A FPGA (Xilinx Virtex series) for zero suppression, feature extraction (online pulse shape analysis, summation), event building, formatting, trigger input handing, output buffering (and send to SUR) Similar to TRU in PHOS/EMCAL.

FEE & SRU Use SRU as EMCAL/DCAL/(TPC) will do. 13 FEE & SRU Use SRU as EMCAL/DCAL/(TPC) will do. developed by RD51+ALICE project TTCrx interface for trigger handling 10 GBE, SPF, optical fiber Master for the slow control of FEEcards

14 Scheme: FEE and SRU

Readout for Strips Strip specifications: Requirements: 15 Readout for Strips Strip specifications: Production of Strip by Hamamatsu is on going Single sided, 6 inch wafer, 525um thickness, 0.7mm pitch Readout (pad) into 2 direction Requirements: Dynamic range [dE]: 0.15MeV (MIP) – 200MeV (500GeV) Dynamic range [C] : 6fC – 10pC Alternative solution instead of strips: Use pixel layers (MIMOSA type) need to evaluate the performance At least to me, following performances are being awaited Singe pi0 reconstruction, Two gamma separation, Shower reconstruction (energy/position) under p+p/p+A/A+A condition

Electronics for Strip PACE-III chips (LHCf and CMS preshower counters) 16 Electronics for Strip PACE-III chips (LHCf and CMS preshower counters) Dynamic range : 0.1MIP – 400MIP (0.4fC – 1.6pC) 25ns peaking. 32ch. 192 AMC (5usec). 600mW /chip Need L1 to read from AMC (3 samples). MEB < 16 L1A Need to enlarge the dynamic range (x10), 32ch->64ch Another chips with large range?

Jig for assembling towers-I 17 Jig for assembling towers-I First prototype jig for building towers came to lab. Summing board + HIROSE FPC/FFC connector

Jig for assembling towers-II 18 Jig for assembling towers-II First prototype jig for building towers came to lab.

Jig for assembling towers-III 19 Jig for assembling towers-III First prototype jig for building towers came to lab.

backups

Basic parameters Basic parameters for inputs 19 Basic parameters Basic parameters for inputs http://cdsweb.cern.ch/record/689223/files/INT-1997-13.pdf?version=1 Pi0 and direct photon production cross section in p+Pb and p+p Expected rate (p+p): Inelastic collisions ~40kHz pi0 (pt>2GeV, h=3-4) ~200Hz rejection=200 Expected rate (p+A) ~200kHz Pi0 (pt>2GeV, h=3-4) ~4kHz rejection=50 eta=3-4 eta=3-4 Direct photon p+p@8TeV p+Pb@8TeV p+p@8TeV Decay photon Pi0, g from pi0 Annual Year yield (DAQ efficiency not included)

18 FoCAL Trigger Let’s discuss the possible scenario for the FoCAL trigger For the study of CGC, physics associated with small-x and smaller Q2 might be interesting. Direct photons/pi0-jet correlation What FoCAL triggers for what? Single photons (isolation?) pi0-jet trigger in conjunction with the central barrel How beneficial of the trigger? Event rejection Need to do quantitative simulations/calculations

Hardware for FoCAL Trigger 20 Hardware for FoCAL Trigger More detail will be determined according to quantitative studies by simulations. Possible scenario for the trigger logic. As EMCal/PHOS are doing, take 2x 2 analog sum, digitize 2x2 analog sum and take 4x4 sliding summation. In terms of the multiplicity, particle density in central p+A collisions is 0.04/cm2. This means 1 particle per 5x5 cm2. 8 x 8 summation might be disfavored. 2x2 or 4x4 might be the candidate. Longitudinal summation in the bus. TRU FADC (40MSPS) ALTRO ASIC 32 4 32 4 Fast shaper 32 FPGA 64 4 32 4 L0/L1 V->I 2x2 sum 16ch