Dept. of Electronics. & Info. Eng. Prof. Jongbok Lee

Slides:

Advertisements

Similar presentations

VHDL 5 FINITE STATE MACHINES (FSM) Some pictures are obtained from FPGA Express VHDL Reference Manual, it is accessible from the machines in the lab at.

Advertisements

Tutorial 2 Sequential Logic. Registers A register is basically a D Flip-Flop A D Flip Flop has 3 basic ports. D, Q, and Clock.

VHDL Lecture 1 Megan Peck EECS 443 Spring 08.

COE 405 VHDL Basics Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Dr. Aiman H. El-Maleh Computer Engineering.

Synchronous Sequential Logic

Registers and Counters. Register Register is built with gates, but has memory. The only type of flip-flop required in this class – the D flip-flop – Has.

28/10/2007DSD,USIT,GGSIPU1 Latch & Register Inference.

L18 – VHDL for other counters and controllers. Other counters  More examples Gray Code counter Controlled counters  Up down counter  Ref: text Unit.

Latches and Flip-Flops

1 VLSI DESIGN USING VHDL Part II A workshop by Dr. Junaid Ahmed Zubairi.

Ring Counter Discussion D5.3 Example 32. Ring Counter if rising_edge(CLK) then for i in 0 to 2 loop s(i)

Mridula Allani Fall 2010 (Refer to the comments if required) ELEC Fall 2010, Nov 21(Adopted from Profs. Nelson and Stroud)

1 VLSI DESIGN USING VHDL A workshop by Dr. Junaid Ahmed Zubairi October 2002.

Counters Discussion D5.3 Example 33. Counters 3-Bit, Divide-by-8 Counter 3-Bit Behavioral Counter in Verilog Modulo-5 Counter An N-Bit Counter.

Latches and Flip-Flops Discussion D4.1 Appendix J.

Shift Registers Discussion D5.2 Example Bit Shift Register qs(3) qs(2) qs(1) qs(0) if rising_edge(CLK) then for i in 0 to 2 loop s(i) := s(i+1);

Random-Access Memory Distributed and Block RAM Discussion D10.3 Example 41.

Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal.

VHDL Introduction. V- VHSIC Very High Speed Integrated Circuit H- Hardware D- Description L- Language.

VHDL IE- CSE. What do you understand by VHDL??  VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language.

Designing of a D Flip-Flop Final Project ECE 491.

ENG2410 Digital Design LAB #6 LAB #6 Sequential Logic Design (Flip Flops)

ENG241 Digital Design Week #8 Registers and Counters.

CPE 626 Advanced VLSI Design Lecture 6: VHDL Synthesis Aleksandar Milenkovic

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Topics VHDL register-transfer modeling: –basics using traffic light controller; –synthesis.

Hardware languages "Programming"-language for modelling of (digital) hardware 1 Two main languages: VHDL (Very High Speed Integrated Circuit Hardware Description.

Feb. 26, 2001Systems Architecture I1 Systems Architecture I (CS ) Lecture 12: State Elements, Registers, and Memory * Jeremy R. Johnson Mon. Feb.

VHDL Discussion Sequential Sytems. Memory Elements. Registers. Counters IAY 0600 Digital Systems Design Alexander Sudnitson Tallinn University of Technology.

04/26/20031 ECE 551: Digital System Design & Synthesis Lecture Set : Introduction to VHDL 12.2: VHDL versus Verilog (Separate File)

CEC 220 Digital Circuit Design VHDL in Sequential Logic Wednesday, March 25 CEC 220 Digital Circuit Design Slide 1 of 13.

CDA 4253 FPGA System Design Sequential Circuit Building Blocks Hao Zheng Dept of Comp Sci & Eng USF.

Lecture 10 Sequential Circuits The Basic Latch

Dept. of Electrical and Computer Eng., NCTU 1 Lab 8. D-type Flip-Flop Presenter: Chun-Hsien Ko Contributors: Chung-Ting Jiang and Lin-Kai Chiu.

D Flip Flop. Also called: Delay FF Data FF D-type Latches ‘Delayed 1 Clock Pulse’

ECE DIGITAL LOGIC LECTURE 20: REGISTERS AND COUNTERS Assistant Prof. Fareena Saqib Florida Institute of Technology Fall 2015, 11/19/2015.

INF H131 Clock and Reset Unit (CRU) module library ieee; use ieee.std_logic_1164.all; entity cru is port ( arst : in std_logic; -- Asynch. reset.

George Mason University Behavioral Modeling of Sequential-Circuit Building Blocks ECE 545 Lecture 8.

Registers and Counters Discussion D8.1. Logic Design Fundamentals - 3 Registers Counters Shift Registers.

Sequential statements (1) process

Week #6 Sequential Circuits (Part A)

LAB #6 Sequential Logic Design (Flip Flops, Shift Registers)

Class Exercise 1B.

Registers and Counters

EMT 351/4 DIGITAL IC DESIGN Week # Synthesis of Sequential Logic 10.

B e h a v i o r a l to R T L Coding

Dept. of Electronics & Info. Eng. Prof. Jongbok Lee

Introduction Introduction to VHDL Entities Signals Data & Scalar Types

Chapter 5. Code converter

CHAPTER 17 VHDL FOR SEQUENTIAL LOGIC

Part IV: VHDL CODING.

Dept. of Electronics & Info. Eng. Prof. Jongbok Lee

ECE 3130 – Digital Electronics and Design

Dept. of Info. & Comm. Eng. Prof. Jongbok Lee

Latches and Flip-flops

VHDL 5 FINITE STATE MACHINES (FSM)

Sequential-Circuit Building Blocks

Field Programmable Gate Array

Field Programmable Gate Array

CHAPTER 17 VHDL FOR SEQUENTIAL LOGIC

RTL Style در RTL مدار ترتيبي به دو بخش (تركيبي و عناصر حافظه) تقسيم مي شود. مي توان براي هر بخش يك پروسس نوشت يا براي هر دو فقط يك پروسس نوشت. مرتضي صاحب.

Non-synthesizable VHDL Poor Design Practices

ECE 3130 – Digital Electronics and Design

Behavioral Modeling of Sequential-Circuit Building Blocks

Sequntial-Circuit Building Blocks

1) Latched, initial state Q =1

74LS273 D Flip Flops and 74LS Mux Zachary Ryan

Sequntial-Circuit Building Blocks

(Sequential-Circuit Building Blocks)

(Simple Testbenches & Arithmetic Operations)

EEL4712 Digital Design (Midterm 1 Review).

Presentation transcript:

Dept. of Electronics. & Info. Eng. Prof. Jongbok Lee Ch. 9 Flip Flops & Clocks Dept. of Electronics. & Info. Eng. Prof. Jongbok Lee

% The Usage of Clocks declaration The expression of Rising Edge clk : in std_logic; The expression of Rising Edge if (clk’event and clk=‘1’) then if rising_edge(clk) then The expression of Falling Edge if (clk’event and clk=‘0’) then if falling_edge(clk) then

% Emulation using a clock Back ground In FPGA, the input pin for using a clock is determined. Clock input pin must be specially treated using component ibuf and component bufg.

How-to Package & library declaration: erase the comment on following two lines. library unisim; use unisim.Vcomponents.all; Declare ibuf & bufg in the architecture declaration part Component instantiation in the architecture main body component ibuf port (i:in std_logic; o : out std_logic); end component; component bufg port (i:in std_logic; o: out std_logic); end component; u1 : ibuf port map (i=>user_clk, o=>tmp); u2 : bufg port map (i=>tmp, o=> real_clk);

1. D Flip Flop Function Types The data applied to D input is transferred to output by the clock signal. Used for registers, small memories. Types simple D flip flop input : d, clk output : q D flip flop with synchronous/asynchronous reset intput : d,clk,reset

[1] A Simple D Flip Flop (for simulation) enitity dff is port ( d,clk : in std_logic; q : out std_logic); end dff; architecture behavioral of dff is begin process(clk,d) if (clk’event and clk=‘1’) then q <= d; end if; end process; end behavioral;

[2] A Simple D Flip Flop (for emulation) library unisim; use unisim.vcomponents.all; enitity dff is port ( d,clk : in std_logic; q : out std_logic); end dff; architecture behavioral of dff is component ibuf port (i:in std_logic; o:out std_logic); end component; component bufg port (i:in std_logic; o:out std_logic); end component; signal tmp,rclk : std_logic; begin u1 : ibuf port map (i=>clk,o=>tmp); u2 : bufg port map (i=>tmp, o=>rclk); process(rclk,d) if (rclk’event and rclk=‘1’) then q <= d; end if; end process; end behavioral;

signal pin no. clk M14 d G1 q A12 키트 연결 dff.ucf NET "clk" LOC = "M14" ; NET "d" LOC = "G1" ; NET "q" LOC = "A12" ; NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; signal pin no. clk M14 d G1 q A12 P16 D9 C9 C12 B13 B14 A14 A12 R16 C15 B16 G14 G15 L13 M14 G1 % 실험 G1을 내리고(d=1) M14를 올렸다 내리면(clk:0->1) A12가 켜짐(q=1)