14NM FINFET IN MICROWIND

14-NM FINFET IN MICROWIND An application note on 14-nm FinFET has been released in June 2017 Microwind 3.8 has been configured to simulate FinFET design Technology parameters are close to 14-nm from Intel The rule file cmos14nm.RUL is available at www.microwind.org

14-NM MAKES THE BREAKING NEWS Feb. 2015 - http://phandroid.com/2015/02/16/exynos-7-14nm/

EXAMPLES OF 14-NM PROCESSORS 14-nm Exynos by Samsung™ 14-nm Xeon by Intel ™ 14-nm Snapdragon by Qualcomm™ 14-nm Zen Processor by AMD™

65nm 28nm 14nm Power -50% -80% 65nm 28nm 14nm SCALE DOWN BENEFITS Smaller Faster Less power consumption Cheaper (if you fabricate millions) 65nm 28nm 14nm Power -50% -80% 65nm 28nm 14nm

MICROWIND FINFET Microwind’s FinFET implementation based on a selection of 10 scientific publications The FinFET is used starting 14-nm node Layout, size and performances inspired from “average” 14-nm FinFET Scaling to 10-nm & 7-nm nodes Application note in progress Standard cell level parasitics assessment in 20nm BPL and 14nm BFF P. Schuddinck, IEDM 2012 3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits Ajay N. Bhoj, IEEE VLSI, Vol 21, N°11, 2013

The FinFET device has a different layout style than the MOS device FROM MOSFET TO FINFET >= 20nm <= 14nm The FinFET device has a different layout style than the MOS device Instead of a continuous channel, the FinFET uses fins FinFET provides the same Ion current at a smaller size FinFET provides lower leakage current Ioff at the same Ion fins

New screen in Microwind INTRODUCING THE FINFET MOS Parameter Typical value Width (W) 6 - 12 λ Length (L) 2 λ New screen in Microwind FinFET Parameter Typical value Number of fins (NF) 2 - 5 Fin pitch (PF) 6 λ Fin thickness (TF) 1 λ Fin length or gate length (LG) 2 λ

3D OF FINFET USING MICROWIND Microwind enables a 3D view of the FinFET P-FinFET Fin 4 Drain Fin 3 Fin length (LG) Fin 2 Fin thickness (TF) Source Fin 1 Fin height (HF) Gate N-FinFET

FIN from Drain to Source Total equivalent channel width Weq FIN BENEFITS The total equivalent channel width is higher in FinFET than in MOSFET Weq = (2*HFIN+TFIN)*NFIN NFIn is the number of fins (2 to 4 usually) Benefit 30-50% in current drive for the same area Fin thickness (TFIN) Gate Fin height (HFIN) FIN from Drain to Source Total equivalent channel width Weq MOS Fin Ioff Patton, Evolution and Expansion of SOI in VLSI Technologies: Planar to 3D, IEEE International SOI Conference 2012 Ion

Gate oxide (Hf02) EQUIVALENT GATE OXIDE EOT = 𝑛. 𝑑 SiO2  + 𝑇h ×  𝜖 SiO2 / 𝜖 HfO2 EOT is around 0.9 nm for 14-nm 0.65 nm for 7-nm 𝑑 SiO2 distance between 2 SiO2 atoms 0.2 nm n is the number of SiO2 atoms 3 in 14-nm 2 in 7-nm Th is the thickness of HfO2 3 nm in 14-nm (12 atoms) 1.4 nm in 7-nm (7 atoms) 𝜖 SiO2 = 4 𝜖 HfO2 = 20 Gate oxide (Hf02)

What is the equivalent width (14-nm) ? HFIN 40nm WFIN 8nm NFIN=12 Answer: around 1mm What is the equivalent width (14-nm) ?

GENERATING A FINFET Fin Length, equal to gate length, (LG) is 2 lambda (16 nm) by default Fin thickness (TF) is set to 1 lambda (8 nm) Fin pitch (PF) is set to 6 lambda (48nm) Number of fingers (NFIN) range from 1 to 4 usually FinFET comme with dummy gates for manufacturability

GENERATING A FINFET HD: High density drawing style : 2 fins HP : High performance drawing style : 4 fins 1 fin exists in very high density cells such as SRAM FinFET with more than 4 fins drive string currents

FIN, GATE AND METAL PITCH Illustration of fin, gate and metal 1 pitch for 14-nm technology

Ion Ion Ioff Ioff FINFET MANUFACTURABILITY Fins should be aligned and horizontal, regular pitch 6  (1+5) Non-aligned fins may lead to gate distortion and current performance spread Ion Ion Ioff Ioff

FINFET MANUFACTURABILITY Gates should be aligned and vertical, regular pitch with 8  minimum (2+6)

FINFET CURRENT DRIVE In 14-nm, 12 fins are needed to have an equivalent width around 1µm One fin has 2*HFIN+WFIN equivalent channel width Ion should be around 1.3mA for Weq=1µm A MosFET design would require nearly twice the area

FINFET CURRENT DRIVE INTEL’s 14++nm CMOS technology: Ion 2mA/µm with Ioff 10nA, the word’s highest performance transistors Ioff Ion Dr. Ruth Brain, 14 nm technology leadership, Intel, TECHNOLOGY AND MANUFACTURING DAY

Very high speed - Super low VT 0.22 Timing critical functions FINFET OPTIONS ACRONYM MEANING THRESHOLD VOLTAGE USED FOR DRAWBACK LL - RVT Low leakage, Regular VT 0.32 Default Slow HS - LVT High speed - Low VT 0.28 High speed functions Leakage current VHS – SLVT (n.a) Very high speed - Super low VT 0.22 Timing critical functions Very high leakage & power consumption Jin, M., Reliability characterization of 10nm FinFET technology, IEDM 2016

1.5 mA/µm 1.3 mA/µm LL – RVT HS – LVT FINFET DRIVE IN MICROWIND The BSIM4 model has been tuned to Ion=1.5mA @10nA for Ion=1.3mA @1nA for High Speed, Low VT (HS – LVT) Ion=1.2mA @1nA for Low Leakage, regular VT (LL – RVT) Not as impressive as Intel’s 14++, but close to 14nm first generation 1.3 mA/µm LL – RVT HS – LVT

Average IDS during switching ION, IDSAT, IEFF Average IDS during switching 𝐼 𝑶𝒏 = 𝐼 𝑫𝑺𝑨𝑻 = 𝐼 𝐷𝑆 ( 𝑉 𝐺𝑆 = 𝑉 𝐷𝐷 , 𝑉 𝐷𝑆 = 𝑉 𝐷𝐷 ) 𝐼 𝑒𝑓𝑓 = 𝐼 ℎ𝑖𝑔ℎ + 𝐼 𝑙𝑜𝑤 2 𝐼 𝑙𝑜𝑤 = 𝐼 𝐷𝑆 ( 𝑉 𝐺𝑆 = 𝑉 𝐷𝐷 2 , 𝑉 𝐷𝑆 = 𝑉 𝐷𝐷 ) 𝐼 ℎ𝑖𝑔ℎ = 𝐼 𝐷𝑆 ( 𝑉 𝐺𝑆 = 𝑉 𝐷𝐷 , 𝑉 𝐷𝑆 = 𝑉 𝐷𝐷 2 ) ION never reached IEFF IEFF = 0.73 mA

FINFET EXAMPLE Hand-made FinFET inverter 2-fin strategy for high density Dummy poly gates on both sides for manufacturability

3-STAGE RING OSCILLATOR 3 inverters connected for a free oscillation Use 4 fins for fast switching Investigate « high-speed » option Investigate « boost » on VDD

3-STAGE RING OSCILLATOR LL : 190 GHz 0.12 mW VDD = 0.80V HS: 204 GHz 0.15 mW VDD = 0.80V HS Max : 230 GHz 0.27 mW VDD = 0.90V

3-STAGE RING OSCILLATOR At same power dissipation, the oscillation is 4 times faster 14-nm @0.8V FinFET Speed x 4 at same power Power /3 at same speed 20-nm @0.9V MosFET High speed Low leakage

VARIABILITY Monte-Carlo analysis with 100 sets of technology parameters

CONVERT MOSFET TO FINFET The command Edit > Convert into FinFET creates fins from N-diffusion Only works for vertical gates Generate fins according to fin pitch (r308)

COMPILE LOGIC GATES The cell compiler enables direct logic gate compilation, including dummy gates, 2 or 4 fins. Some basic cells are accessible within a click

COMPILE LOGIC GATES Nor2 2 fins And3 4 fins

COMPILE COMPLEX GATES A|(B&C) : yes we can (but not always win…)

INTERCONNECTS Generate a full stack of metal layers with min width and min spacing (min pitch) Edit > Generate > Bus Select “all layers” Select length 1µm as many available data are given in af/µm, Ω/µm, aH/µm

10NM INTERCONNECTS Air Metal 8 Metal 7 Metal 5,6 Metal 3,4 Metal 1,2 Gates Substrate

CAPACITANCE Capacitance with upper layer Coupling capacitance Capacitance with lower layer

Simple, Double, Quadruple (and so does the cost..) PATTERNING Pitch (nm) λ >120 110 100 90 80 70 60 50 40 30 20 Patterning Single Double Quad 45-nm All 32-nm 18 M3-M8 M1-M2 Gate 20-nm 12 M7-8 M5-M6 M3-M4 14-nm 8 10-nm 6 7-nm 4 SINGLE DOUBLE QUADRUPLE Complexity Integration Simple, Double, Quadruple (and so does the cost..)

𝑖𝑓 𝐵=1, 𝑋𝑜𝑟= 𝐴 , 𝑒𝑙𝑠𝑒 𝑋𝑜𝑟=𝐴 6T – Bug ! Very large delay XOR GATE 6-Transistor implementation do not work correctly in nano-CMOS 𝑖𝑓 𝐵=1, 𝑋𝑜𝑟= 𝐴 , 𝑒𝑙𝑠𝑒 𝑋𝑜𝑟=𝐴 6T – Bug ! Very large delay

𝑋𝑂𝑅=𝐴 𝐵 +𝐵 𝐴 = 𝐴 𝐵 × 𝐵 𝐴 16T - safe XOR GATE 16-Transistor implementation used in Microwind compilation of XOR gates 𝑋𝑂𝑅=𝐴 𝐵 +𝐵 𝐴 = 𝐴 𝐵 × 𝐵 𝐴 16T - safe

XOR DESIGN 16-T XOR GATE : 2 fins High density 7ps delay worst case (Low leakage)

XOR DESIGN 16-T XOR GATE : 4 fins High performance 5 ps delay LL, 4 ps delay HS option Firestarter: 3.3 ps (HS, VDD boost 0.95V)

Shared supply contacts 14NM 6T MEMORY 6T-Static RAM memory in 14-nm : 0.050µm2 Bonding box 328 x 129 nm Single fin inverter Double fin pass transistor Shared Data contact Shared supply contacts

10NM FINFET IN MICROWIND

10-NM FINFET IN MICROWIND An application note on 10-nm FinFET has been released in June 2017 Microwind 3.8 has been configured to simulate FinFET design Technology parameters are close to 10-nm available publications (Intel) The rule file cmos10nm.RUL is available at www.microwind.org

10-NM & 7-NM CHIPS IBM, GlobalFoundries, Samsung, SUNY first 7-nm testchip Samsung Exynos 8895 in 10-nm Qualcomm Snapdragon 635 in 10-nm

10-NM FINFET Intel has released information about 10-nm FinFET technology The fin pitch is decreased according to scale down The fin height is increased for increased current drive Mistry, K. (2017). 10 nm technology leadership, Technology and Manufacturing Day, Intel. 2017.

10-NM FINFET TECHNOLOGY An application note has been released in June 2017 on 10-nm technology Key features of the 10-nm node are described

EQUIVALENT WIDTH In microwind: 10-nm FinFET almost unchanged: HFIN=40 nm, WFIN reduced to 6nm HFIN 40nm WFIN 6nm NFIN=12 Answer: around 1mm

10-NM n-FinFET High Speed Low VT Ion: 1.6mA Low leakage Regular VT Weq=1µm Low leakage Regular VT High Speed Low VT Ioff : 4nA Ioff: 30nA

10-NM p-FinFET Ion: 1.4 mA High Speed Low VT Ion: 1.2 mA Low leakage Regular VT P-FinFET Weq=1µm Low leakage Regular VT Ioff : 2nA Ioff: 12nA

All metal layers at minimum width and minimum spacing 10-NM INTERCONNECTS Metal 8 All metal layers at minimum width and minimum spacing Metal 7 Metal 5,6 Metal 3,4 Metal 1,2 Gates Substrate

10-NM RING OSCILLATOR Minimum Process Voltage Temperature variations (PVT) Access through Simulation > Simulation parameters Direct access in simulation menu through Process Var.

10-NM RING OSCILLATOR Typical 240 GHz Typ VDD = 0.70V Typ T°=25°C Typ VT, U0 Minimum 150 GHz Low VDD = 0.60V High T°=125°C High VT, Low U0 Maximum 290 GHz High VDD = 0.81V Low T°=-50°C Low VT, High U0

6T-Static RAM memory in 10-nm, high density : 0.024 µm2 10NM SRAM 6T-Static RAM memory in 10-nm, high density : 0.024 µm2 Shared Data contact Bonding box 246 x 96 nm Single fin inverter Double fin pass transistor Shared supply contacts

7NM FINFET IN MICROWIND

7NM APPLICATION NOTE An application note on 7-nm FinFET has been released in June 2017 Microwind 3.8 has been configured to simulate FinFET design Technology parameters are close to 7-nm preliminary information The rule file cmos7nm.RUL is available at www.microwind.org

In Microwind: 7-nm FinFET : HFIN = 35 nm, WFIN = 4 nm EQUIVALENT WIDTH In Microwind: 7-nm FinFET : HFIN = 35 nm, WFIN = 4 nm WFIN 4 nm HFIN 35 nm Answer: around 1mm NFIN=14

7-NM N-FinFET Ion: 1.7 mA N-FinFET 14 fins Weq=1µm High Speed Low VT Low leakage Regular VT Ion: 1.4 mA VDD=0.65 V Low leakage Regular VT High Speed Low VT Ioff : 1 nA Ioff: 10 nA

7-NM P-FinFET Ion: 1.5 mA P-FinFET 14 fins Weq=1µm Ion: 1.2 mA High Speed Low VT Low leakage Regular VT VDD=0.65 V High Speed Low VT Low leakage Regular VT Ioff : 1 nA Ioff: 10 nA

VTO for 2 lambda HV LL - RVT HS - LVT P-channel FinFET FINFET THRESHOLD VOLTAGE VTO as described in the BSIM4 model corresponds to long channel MOS VTO for short channels is always lower Parameters DVT0 and DVT1 used to tune VTO (length) VTO for 2 lambda HV LL - RVT HS - LVT P-channel FinFET N-channel FinFET

XOR 2 INPUTS 16-T XOR GATE : 2 fins High density 4.5 ps delay worst case (Low leakage)

10-NM RING OSCILLATOR Typical 240 GHz Typ VDD = 0.70V Typ T°=25°C Typ VT, U0 Minimum 150 GHz Low VDD = 0.60V High T°=125°C High VT, Low U0 Maximum 290 GHz High VDD = 0.81V Low T°=-50°C Low VT, High U0

+ 75% performance increase COMPARING 14NM AND 7NM Ring Oscillator 2 Fins 3 stages Fan-Out 3 (FO3) 7-nm 175 GHz + 75% performance increase 14-nm 100 GHz Min VDD 0.55 V Min VDD 0.50 V VDD 0.85 V VDD 0.65 V

High quality inductor, supply, flip chip connection 7NM INTERCONNECTS Metal 8 High quality inductor, supply, flip chip connection Metal 7 Supply routing Metal 5,6 Long interconnects Metal 3,4 Medium interconnects Metal 1,2 Short interconnects FinFET Gates Substrate

6T-Static RAM memory in 7-nm, high density : 0.010 µm2 7NM 6T HIGH DENSITY SRAM 6T-Static RAM memory in 7-nm, high density : 0.010 µm2 Shared Data contact Bonding box 164 x 64 nm Single fin inverter Double fin pass transistor Shared supply contacts

INVESTIGATE TECHNOLOGIES A quick access to technology is proposed in Simulation Parameters MosFET technologies range from 0.18µm to 20nm FinFET technologies (red) start from 14nm MosFET and FinFET designs are not compatible