Introduction to Digital System Design Final Exam Review Notes

ECE 270 Comprehensive Final Date: Thursday May 4 Time: 3.30 – 5.30 pm Place: STEW 183 Material covered: Modules 1-4 IMPORTANT: Be sure you bring your PUID card and know your SEATING ASSIGNMENT

Restrictions Closed book and notes Supplied pencils must be used Use of TI-30II XS calculator (only) allowed Electronic devices may not be used Earphones/earbuds may not be worn Cell phones must be turned off and put away Caps may not be worn during the exam No pen cameras or watch cell phones allowed MUST HAVE PUID CARD Makeup exams must be scheduled in advance

Learning Outcomes A student who successfully fulfills the course requirements will have demonstrated: an ability to analyze and design CMOS logic gates an ability to analyze and design combinational logic circuits an ability to analyze and design sequential logic circuits an ability to analyze and design computer logic circuits an ability to realize, test, and debug practical digital circuits

Learning Outcome Assessment You will earn 1% bonus credit for each course outcome you successfully demonstrate TWO opportunities will be provided to demonstrate each course outcome: A score of 60% on either the Primary Assessment of Outcomes 1 through 4 or the corresponding Final Assessment of that outcome will be required for successful demonstration A score of 60% on each lab experiment or a score of 60% on the Lab Practical Exam will be required for successful demonstration of Outcome 5

Grade Determination Bonus Exercises “BON” ∆1% 90% to 100% A-, A, A+ 80% to 90% B-, B, B+ 70% to 80% C-, C, C+ 60% to 70% D-, D, D+ < 60% F Grade Determination Bonus Exercises “BON” ∆1% Class Participation (discussion forums, iClickers) “CP” 4.0% Homework Exercises “HW” and Lab Notebook Maintenance 10.0% Lab Experiments “EXP” (13 @ 1.5%) 19.5% Lab Quizzes “QUZ” (13 @ 0.5%) 6.5% Lab Practical Exam “LPE” Primary Outcome Assessment Exams “POA” (4 @ 10%) 40.0% Final Outcome Assessment “FOA” (4 @ 2.5%) ∆2% Outcome Demonstration Bonus “LODBN” (5 @ 1%) 100+∆%

Grade Determination Calculation of Raw Weighted Percentage: RWP then “curved” (mean-shifted) with respect to upper percentile of class, yielding the Normalized Weighted Percentage (NWP) Windowed Standard Deviation (WSD) for class is calculated based on statistics of “middle” 90% of class Cutoff Width Factor (CWF) is then max(WSD,10), i.e., the nominal cutoffs are 90-80-70-60 for A-B-C-D, respectively

± Grading Visualization (CWF=10) B A + + + + - - - - 30% 40% 30% 30% 40% 30% 30% 40% 30% 30% 40% 30%

Borderline Cases A “borderline” is officially defined as an NWP within 0.5% of a letter grade cutoff Before course grades are assigned, the course instructors will carefully examine all such cases to determine if the next higher grade is warranted IMPORTANT NOTE: The “next higher grade” is NOT AUTOMATICALLY GUARANTEED!! Once course grades are assigned, they are FINAL and will NOT be changed

Learning Objectives As part of faculty participation in the Purdue IMPACT initiative, a detailed set of learning objectives have been developed based on Bloom’s taxonomy The goal is to teach intentionally and test intentionally based on the stated outcomes and objectives A list of learning objectives is included in the Lecture Summary Notes for each outcome as well as the Class Presentation Slides Use the list of learning objectives as a guide for reviewing the lecture material and homework problems.

Possible Questions – Outcome 1 Convert unsigned numbers from one base to another Graphically transform a logic circuit from one set of symbols to another through successive application of DeMorgan’s Law Find the dual or the complement of a given Boolean function Calculate fan-out and D.C. noise margin for a hypothetical logic family Calculate value of LED current limiting resistor Determine transition times and propagation delays from a timing chart Calculate the “on” resistance of an active N- or P-channel device

Possible Questions – Outcome 1 Estimate rise and fall time of a CMOS gate output as a function of its capacitive load and “on” resistance Describe what happens when a gate output is loaded beyond its rated specifications Describe what happens when “non-ideal” voltages are applied to a CMOS gate input Calculate value of pull-up resistor for logic circuit containing open-drain gates Describe what happens as multiple open-drain devices connected in parallel are turned on/off Determine relative power dissipation of CMOS circuits as a function of power supply voltage and clock speed

Possible Questions – Outcome 2 Graphically transform a logic circuit from one set of symbols to another through successive application of DeMorgan’s Law Express a given Boolean function a variety of ways, e.g., as an ON-set, as an OFF-set, as a canonical sum-of-products, etc. Find the dual or the complement of a given Boolean function Determine a minimal sum-of-products or product-of-sums expression for a given Boolean function using a K-map Realize a given Boolean function using either a two-level NAND circuit or two-level NOR circuit, and compare the cost Realize a given Boolean function using a single-level open-drain NAND circuit Realize a given Boolean function using a circuit that is free of hazards Sketch a timing diagram that depicts the relationship among logic signals Simplify a function in terms of XOR/XNOR operators

Possible Questions – Outcome 2 Identify macrocell characteristics Realize combinational functions in ABEL Knowledge of basic ABEL source file structure Knowledge of basic keywords and extensions Knowledge of ranges, sets, and relations Knowledge of attribute suffixes Knowledge of equation syntax Knowledge of truth table format Knowledge of report content/interpretation Compare discrete realizations with PLD-based realizations Realize decoder building blocks in ABEL Realize encoder building blocks in ABEL Realize tri-state output capability in ABEL Realize multiplexer building blocks in ABEL Realize XOR functions in ABEL

Possible Questions – Outcome 3 Describe the difference between a latch and a flip-flop Identify all latch and flip-flop timing parameters Describe the phenomenon of metastability Perform basic sequential circuit analysis (e.g., an S-R latch) Write next state equations Construct a present state - next state table Construct a state transition diagram Construct a timing chart Analyze sequential circuits containing S-R, D, and T flip-flops

Possible Questions – Outcome 3 Describe the difference between a Mealy Model and a Moore Model Draw a state transition diagram using either a Mealy Model or a Moore Model Synthesize the characteristic equation of any type of flip-flop (S-R, D, T) from any other type of flip-flop Design a clocked synchronous state machine using edge-triggered D flip-flops Identify all the macrocell-related attribute suffixes in a complex PLD Write an ABEL program that realizes a clocked synchronous state machine (sequence recognizer, counter/shift register, sequence recognizer)

Possible Questions – Outcome 4 Perform radix addition and subtraction Convert numbers from one sign notation system to another Perform sign extension of radix operands Derive equations for a half-adder and full-adder Design a two’s complement adder/subtractor with condition code generation circuitry Analyze an arithmetic logic unit (ALU) Design a magnitude comparator circuit (note: may be signed or unsigned) Derive the equations for a carry look-ahead adder Design an unsigned multiplier array circuit Analyze propagation delay of multiplier arrays Implement an unsigned multiplier in ABEL Design a BCD adder/subtractor circuit Implement a BCD adder in ABEL

Possible Questions – Outcome 4 Trace the execution of a machine language program (know what instructions are, how they work, and what they do) Implement simple computer functional blocks (e.g., program counter, instruction register, ALU, stack pointer, IDMS) Analyze the logical behavior of an ABEL-based CLA Implement any of the basic extensions (shift instructions, I/O, transfer-of-control) Complete the system control table for an extended (multi-cycle) instruction set Describe the two possibilities for stack conventions and any tradeoffs between them Implement new instructions (e.g., “pop and add”, “pop and subtract”) Analyze ABEL code for realizing variants of the simple computer