Presented by Ken Chan Prepared by Ken Chan Understanding Signal to Noise Ratio and Noise Spectral Density in high speed data converters TIPL 4703 Hello. Welcome to this presentation which will discuss the concepts of Signal to Noise Ratio and Noise Spectral Density in high speed data converters. Presented by Ken Chan Prepared by Ken Chan

Table of Contents Using NSD in typical application What is SNR Definition of SNR Components of SNR Thermal, Quantization, Jitter Calculation of SNR Jitter Dominated What is NSD Definition of NSD How is NSD different from SNR Components of NSD Same as SNR, just specification is different Using NSD in typical application In band Performance estimate using close in phase noise Out of band emmissions estimate based on out of band phase noise The 1st part of the presentation will go over the concept of Signal to Noise Ratio or SNR, by defining the meaning of SNR. A more detailed examination of the different components that make up the noise portion of SNR will be explored. This includes thermal noise, quantization noise, and jitter of the quantization clock. An example of a calculation of SNR that is dominated by jitter will be provided. The 2nd part of the presentation will examine the concept of Noise Spectral Density or NSD, and describe how this is different from SNR. Finally a design example will be presented which will highlight how NSD can be used to estimate the performance of the output of a DAC as it pertains to noise floor related performance specifications.

What is SNR - Signal-to-Noise Ratio Basics SNR is the ratio of the signal power to the noise power that corrupts the signal. This parameter does not include harmonic distortion. In the time domain: In the frequency domain: Noise Signal Noisy Signal FFT In real systems, signals are generally corrupted by noise which results in a noisy signal. Simply stated, the Signal to Noise Ratio or SNR is the signal power compared to the noise power in a given signal bandwidth. Typically this is calculated by performing a Fast Fourier Transform or FFT and looking at the fundamental signal power and noise floor power in the frequency domain. The Noise floor power is typically the integration of all of the noise within a given frequency bandwidth excluding the fundamental signal and the harmonics of the fundamental. The SNR is then simply the difference between the signal power and the integrated noise floor power. FREQUENCY (Hz) Signal Noise Level

Maximizing the SNR in an ADC SNR can be increased in the following ways: Increase signal power ↑ Full Scale Range (FSR) Decrease noise power ↓ Quantization Noise Clock Jitter ADC Aperture Jitter Thermal Noise Quantization Thermal Since SNR is the difference between the signal power and the noise power, there are only 2 ways to increase the SNR. 1st, The signal power may be increased up to a maximum of the full scale range, increasing the input signal strength above the full scale range is not recommended and will adversely affect the performance of the ADC. The 2nd way to increase SNR is to decrease the noise power. Noise power is typically a result of a combination of quantization noise, Noise caused by clock jitter, noise caused by ADC aperture jitter, and circuit thermal noise. Reducing 1 or all of these noise sources may help to increase the SNR performance. Aperture Jitter Clock Jitter

SNR by Individual Noise Contributors Total SNR can be calculated by the sum of the individual noise sources: SNRQUANT = SNR due to quantization SNRJITTER = SNR due to clock and aperture jitter SNRTHERM = SNR due to thermal and transistor noise Assuming that the signal power is kept constant at a fixed level, the SNR can be estimated by looking at the noise power contribution from each of the noise sources. Each of the noise power sources can be treated independently. The 3 different noise power sources are Quantization noise, Clock jitter noise, and Thermal and transistor noise. Design choices such as ADC selection will include N-bits quantization noise, ADC aperture jitter, and the thermal noise of the ADC design. Sampling clock choices will result in clock Jitter noise and the choice of the sampling rate of the ADC will generally dictate the bandwidth over which the noise is integrated. In general this is usually the 1st Nyquist up to Fs/2. Design Choice Effect on Noise ADC Selection N-bits affects quantization noise, aperture jitter and thermal noise by design Sampling Clock Selection Clock jitter Sampling Rate Bandwidth over which noise is distributed

Quantization Noise and SNR SNR due to quantization error, assuming a sine wave input: How to determine the required ADC resolution? An N-bit ADC determines the maximum possible SNR for the system Practically, an ADC’s SNR is limited by other factors: Sampling clock jitter ADC jitter and thermal noise Other system noise sources Over-sampling rate and application channel bandwidth Example: 14-bit converter where N=14: The quantization error can be calculated based on the theoretical quantization error assuming a sinewave input. This is given by 6.02dB per bit plus 1.76 dB. This determines the maximum possible SNR for N number of bits. In a real ADC there are other limiting factors such as sampling clock Jitter, ADC aperture jitter and thermal noise, other system noise sources, the oversampling rate of the converter, and the application channel bandwidth.

Transistor and Thermal Noise and SNR Noise Mechanism α Spectral Profile Source Cause Shot IDC white pn-junctions DC bias current is not constant Flicker 1/f Active devices Carriers are “trapped” and released in a semiconductor Thermal T resistors Thermal excitation of carriers in a conductor There are generally 3 sources of circuit noise: Shot noise, Flicker, and Thermal noise. Shot noise is caused by the PN junctions DC bias current and is not constant. It generally has a white noise spectral profile. Flicker noise is caused active circuits and electron carrier movements and generally has a 1/f shape near DC. Thermal noise is caused by the thermal excitation of the resistors and generally has a white noise distribution. Noise in an ADC is dominated by the track and hold circuit thermal noise contribution from the input resistor. Limiting the noise BW to the RC bandwidth, the resulting thermal noise power is given by (kT)/C. Noise in an ADC: Track-and-hold is dominant source Capacitors source no noise Resistor results in “kT/C” noise

Clock Jitter and SNR Clock jitter is the random variation of the clock edge compared to its ideal point in time Theoretical limit of SNR due to jitter: Total jitter is the rms sum of the individual jitter contributions For ADCs, this is generally the external clock jitter and aperture jitter Clock jitter is defined as the random variation of the clock edge compared to its ideal point in time. Variations on this edge will cause the converter to sample the data at non ideal points in time resulting in an error which will contribute to the overall noise and impact SNR. The theoretical limit of SNR due to jitter is defined as the -20*log(2*pi*fin*total jitter). Total jitter is the combined jitter from the clock source and the additional jitter caused by the internal ADC clock circuits – this additional ADC jitter is called the Aperture Jitter.

More on Clock Jitter Clock jitter causes imprecise sampling intervals which results in incorrect sampling instances and therefore errors in the sampled signal Clock jitter has an increased effect at higher input frequencies or higher maximum input slew rates Clock Jitter will cause incorrect samples of the input waveform and will be more prevalent with higher input frequencies. The jitter impact from Jitter can be plotted along side the SNR impact from the thermal noise. At the lower input frequencies, the thermal noise is dominant, while at the higher input frequencies the noise caused by the jitter dominates. The resulting SNR can be thought of as the sum of the SNR impairments from jitter and thermal noise. The plot on the right can be used to illustrate the greater impact that jitter has on higher frequency input signals. It is quite obvious that with lower frequency inputs the possible error is much smaller than with higher input frequencies.

Sources of Clock Jitter The total clock jitter for an ADC is from the aperture jitter and the external sampling clock jitter. Clock jitter is the jitter contribution from the external clock source and can be measured by using a phase noise analyzer Aperture jitter (a.k.a. aperture uncertainty) is the jitter contribution from the ADC, due to the internal clock buffers. This cannot be measured directly using a phase noise analyzer. Example: aperture jitter for the ADS4249 The total clock jitter is determined by rms sum of all individual contributions: As mentioned earlier, the total jitter is a combination of the sampling clock jitter and the aperture jitter. The clock jitter is the contribution from the external sampling clock source and can be measured on a phase noise analyzer. The Aperture Jitter is internal to the ADC clock circuits and cannot be measured by a phase noise analyzer. This is usually characterized by using very clean clocks and high input frequencies to make an estimate of the total jitter based on the measured SNR. Then using the measured external sampling clock phase noise, and estimate of the internal aperture jitter can be derived.

Example Phase Noise Plot Noise Spectral Density (dBc/Hz) This is an example phase noise plot measured on a phase noise analyzer of a sampling clock running at 122.88MHz. The jitter is the integration of the phase noise from 10kHz to 10MHz. In this case the resulting jitter is 299 femto seconds. Frequency (MHz)

Calculating Jitter from Clock Phase Noise Jitter is a result of noise on the sampling clock. Assuming the wideband clock noise is relatively low, then the clock jitter is calculated by integrating the clock phase noise over a specified BW then converting to seconds. Example from previous slide’s phase noise plot: FN = -75.72 dBc/Hz (from 10 kHz to 10 MHz offset) Fclk = 122.88 MHz Where: FN= Phase Noise Power (dBc) f0, f1= frequency limits of integration tj = clock jitter A simple estimation can also be done for the jitter of a clock source if the phase noise plot is available. In the previous example the integrated phase noise between 10kHz and 10MHz is given as -75.72dBc/Hz. With Fclk=122.88MHz, the equation yields a jitter of 299.77 femto seconds.

A different Way to look at Clock Jitter/Noise Some considerations also need to be made for the traditional calculation of SNR based on the jitter and the input signal frequency. A different Way to look at Clock Jitter/Noise 13

Limitation of the Traditional SNR Calculation Due to Jitter The traditional SNR due to jitter equation gives the SNR over the entire Nyquist band, with the jitter measured over a wide clock offset frequency The equation is a function of the analog input frequency and jitter performance If the ADC clock is already fine tuned to the best jitter performance, would the only option left to meet stringent SNR performance is to adjust the input frequency? If so, what is the point of over-sampling ADCs? Previously the theoretical limit of SNR due to jitter was defined as a function of the total jitter and the input frequency. However this implies that the SNR would be the same for an input frequency regardless of the sampling rate. Then the question would be what advantage would over sampling have? Why not use under sampling for every application?

General Equation for ADC SNR It turns out the SNR equation is also a function of clock frequency as well. Recall the jitter equation: If we substitute the jitter equation into the SNR equation, we would get the following: The first term is the inherent integrated noise due to clock noise. The second term is a correction term. This is important to help us understand the performance of over-sampling. If over-sampling is used, the SNR can be improved It turns out that the SNR calculation has some dependence on the sampling clock frequency as well as the input frequency. By substituting the sampling clock jitter equation into the SNR equation, the result is 2 terms. One is based on the integrated phase noise and the 2nd is a term based on the over sampling of the input frequency by the sampling frequency. This correction term allows SNR to be improved if over sampling is used. This is the more general equation for ADC SNR.

Why is the general equation important? The general equation is important because the traditional equation often simplifies the ADC clock noise floor as an uniform white noise. In reality, the ADC clock usually has better noise behavior as the offset frequency increases, and also, the clock is often well filtered. Simplified integrated clock noise Actual phase noise This general equation is important because it gives a better estimate of the SNR performance of the ADC as compared to the traditional equation which uses a simplified estimation of the impact of jitter on the SNR regardless of the sampling frequency or the input signal frequency. In most cases the ADC clock is well filtered and will have better noise at larger frequency offsets.

System Requirement Implication Most importantly, some of the stringent system requirements often are bandwidth specific. I.e. noise spec over a specific bandwidth. For instance, when given a certain blocker signal, the traditional SNR calculation may overestimate the noise over the bandwidth of the wanted signal. This may make jitter specification of the clock impossible to achieve. In some cases the system requirements are often limited to a specific bandwidth, where you only care about the noise floor performance in a specific band. Using the traditional estimate for SNR would require a much more stringent noise spec and may not be achievable or making the solution more complex and more expensive than it needs to be. Looking at the SNR performance at a specific frequency and over a specific bandwidth allows a more optimized system solution.

Experiment Result ADS4149 at 250MSPS Two inputs shown and overlaid: 10MHz and 100MHz Clocking the ADC with a 250MHz tone + 10MHz noise ranging from 240MHz to 250MHz A simple experiment was performed to validate the general ADC SNR equation. A high speed DAC was used to generate a clock with a known exaggerated level of noise around the clock frequency. This was used to drive an ADC and 2 different input signals were sent into the ADC – one tone was at 10MHz and the other was at 100MHz. The resulting signals captured by the ADC are over laid and shown together. (DAC5681 output)

ADC Test Result 20log(250/100) = 8dBc 20log(250/10) = 28dBc As expected the sampling clock phase noise is coupled onto the input signals at 10MHz and 100MHz. The oversampling correction factor improves the SNR at 10MHz by the oversampling ratio of 25x or a 28dB reduction in noise power. Also at 100MHz the oversampling is 2.5x or a reduction in noise power of 8dB.

The next section will discuss the concept of noise floor in the DAC output. Here Noise Spectral Density or NSD is the prefer specification vs SNR. DAC NSD vs SNR 20

SNR Jitter estimate is the same for DACs The total SNR is the vector sum of all individual SNR contributions Similar treatment of clock jitter (integrated phase noise) for SNR limit of DAC sampled system SNRQUANT = SNR due to quantization SNRCLK = SNR due to clock and aperture jitter SNRTHERM = SNR due to thermal and transistor noise The estimate of the SNR for DACs is the same as for ADCs. Similarly the noise floor is made up of contributions from quantization, clock and aperture jitter, and thermal and transistor noise. The jitter limit for SNR is also treated the same way. 21

NSD or SNR? For DACs, generally the noise spectral density (NSD) is more important than overall SNR The shape of the NSD around the carrier must meet mask requirements When SNR is required, customer’s often limit the bandwidth of the transmitted signal by a bandpass or lowpass filter For this reason, newer datasheets report NSD rather than SNR fs = 1GSPS f out = 20MHz DAC output noise is comprised of Quantization noise Thermal noise Jitter noise Data dependent noise For DACs the NSD specification is generally more important than SNR. The shape of the NSD around the carrier must generally meet some transmission mask. Usually when SNR is required, the system will often limit the bandwidth of the signal with a bandpass or low pass filter. The noise floor can then be estimated within the pass band of the filter using the NSD. This is one of the main reasons most new data sheets are reporting NSD (bandwidth limited) vs SNR (1st Nyquist). Signal Noise

Why NSD over SNR? In real systems, there is often tight filtering around the band of interest, where all the noise outside of that band is filtered out. Rather than showing the SNR of the signal in the first Nyquist zone, it is more convenient to show the noise power so that the total noise power in the unfiltered band can be readily calculated For example, consider a DAC3484 running at 1228.8 MSPS with a band of interest of 100 MHz and the following filters: A 614.4-MHz low-pass filter (passing full first Nyquist zone): A 100-MHz low-pass filter: In real systems where there is usually some tight filter around a band of interest and all of the spectrum outside this band is filtered out. Instead of reporting the noise floor for the entire 1st nyquist, it is more convenient to show the noise power per Hz and then estimate the noise floor within the pass band frequencies of the filter. Lets consider a simple example where a DAC3484 is running at 1228.8Msps and it is generating a frequency of interest within the 1st 100MHz. Lets assume the NSD for the DAC3484 is at -160dBc/Hz. If a low pass filter with a frequency corner around Fs/2 (1st Nyquist) is used and the noise floor is calculated for the entire 1st nyquist, the resulting noise floor is -72.12dBFS. However if a low pass filter is used with a corner frequency around 100MHz, then the noise floor within 100MHz is -80dBFS. By looking at the relevant noise floor only, the specification is better by approximately 8dB. 23

Converting NSD to SNR The SNR of the DAC can be calculated from the NSD spec The SNR was traditionally defined as the ratio of the power of the fundamental to the power of the noise integrated over the first Nyquist zone. It can also be calculated directly in dBFS from the NSD in dBc/Hz Example: DAC3484 running at 1.25 GSPS with 10 MHz output The SNR of a DAC can be converted from the NSD specification. The NSD specification is the power of the 1Hz bin. To convert this to SNR over a certain bandwidth, you can simply multiply this by the Hz BW. For the case of the typical SNR which is specified over Nyquist or Fs/2 you would calculate the noise floor based on the NSD, then adding 10 log(Fs/2). This noise floor then can be subtracted from the fundamental signal power to give the SNR. For a real case of the DAC3484, the NSD is specified approximately -160dBc/Hz. If the DAC was sampling at 1.25Gsps. The Noise floor is then calculated as -160dBc/Hz+10log(1.25G/2) = -160dBc+88 dB resulting in an SNR of 72dBFS. 24

NSD to SNR tradeoffs – Jitter/Phase noise SNR estimates based on Jitter are good estimates for SNR for the entire Nyquist band – may be too pessimistic for BW limited applications. SNR estimates based on NSD (typically measured at some MHz offset) do not account for close-in phase noise which could affect inband EVM Useful for out of band estimates like ACPR Also useful for transmit mask requirements Using the clock NSD curve and BW limited noise calculations would be the ideal solution for in-band and out-of-band measurements. In Summary the noise floor of ADCs and DACs can be specified in terms of SNR and NSD. Depending on the application it may be better to use one or the other. It is best to keep in mind some of the important points about NSD and SNR when deciding which to use. SNR estimates based on jitter are convenient estimates for SNR across the entire Nyquist band, however these may be too pessimistic for BW limited applications. SNR estimates based on a NSD measured at an offset frequency do not account for close in phase noise which could impact inband measurements such as %EVM. NSD is useful for out of band estimates such as noise limited ACPR. Using the clock NSD curves and BW limited noise calculations, along with the general equation for SNR would be the ideal solution for inband and out of band estimates. Thank you for watching this presentation.

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