IC Manufactured Done by: Engineer Ahmad Haitham

The First Computers: BDE&ENIAC Vacuum Tube 1946 The Babbage Difference Engine (1832)

The Transistor Revolution First transistor Bell Labs, 1948 ECL 3-input Gate Motorola 1966 1st IC: Bipolar logic 1960’s

Intel 4004 and Pentium (IV) Ps 1971 1K transistors 1 KHz operation 2000 10M transistors 1 GHz operation

Let’s Start The Story !!!

The Silicon Cylinder called Ingot (1 or 2 Meters in Length) Can be Sliced into Hundreds of Smaller Circular Pieces Called Wafers Each Wafer Yields Hundreds or Thousands of Integrated Circuits

Single die Wafer (20 – 30) cm diameter (0.35 – 1.25) mm thick

The surface is free of Scratches and imperfections

Die or IC Fabrication There are 20 to 30 major steps. Each step require five or more operations. Hence, There are 100 to 200 distinct operations to produce a complete IC. Today, IC chip may be up to 30mm on each edge and contains 100 million devices (Transistor, Diode, Resistor,…..etc)

Some of operations

Oxidation: High temperature exposure of silicon to oxygen to form SiO2. Etching: Removal of undesired material with the use of chemical liquid or ionized gas etchant. Diffusion: Doping process to form n-type or p-type material by high temperature exposure to donor or acceptor impurities

Ion Implementation: High-energy bombardment of silicon with donor or acceptor ions from certain accelerator Chemical Vapor Deposition: Material such as metal or oxide are deposited out of a gaseous mixture. Metal can also be deposited using sputtering.

The basic flow in the IC fabrication process

In the PC running certain software Draw a schematic that shows the layout of the geometric patterns that implement The transistors and interconnection

The patterns are converted to a set of masks, one for each major step in The fabrication process. Masks are glass plates with patterns specify the information that will be Printed to the IC in a given step

Photolithography

What is Photolithography What is Photolithography? Process of transferring geometric shapes on a mask to the surface of a silicon wafer

MOSFET Photolithography

Grow SiO2 Deposit polysilicon layer

Wafer is then coated with a polymer which is sensitive to ultraviolet light called a photoresist

There are two basic types of Photoresists, Positive and Negative. Positive Photoresists becomes soluble when exposed with UV light. Negative Photoresists becomes polymerized, and more difficult to dissolve when exposed with UV light.

mask, which will be typically be a chromium pattern on a glass plate Ultraviolet light is then shone through the mask onto the photoresist Positive photoresist

The photoresist is then washed by developer, The resist exposed with UV light will be dissolved

Etch the unwanted polysilicon. Etching is the process where unwanted areas are removed by either dissolving them in a wet chemical solution (Wet Etching) or by reacting them with gases in a plasma to form volatile products (Dry Etching)

Remove the photoresist. The polysilicon pattern is done.

Implant Source & Drain regions of the MOSFET

Implant dopant ions through patterned openings in photoresist

Repeat metal layers.

Create contact windows, deposit & pattern Metal layer

Fabrication Process for DSM CMOS 1- Define Well areas and transistor regions. NMOS is diffused in a p-type well PMOS is diffused in a n-type well 2- Trenches are dug out of the silicon between the wells 3- Oxide is deposited in these stenches using the chemical vapor deposition process (CVD).

4- Define the gate region. Clean thermal oxide is grown in the transistor area by exposure to oxygen in a furnace.

5- Define the poly gate. Again a polycrystalline silicon layer is deposited by CVD 6- Undesired poly and oxide are removed by chemical etching or by plasma (Reactive gas)

7- Form source/drain regions 7- Form source/drain regions. Ion implementation is used for the doping step.

8- Depositing silicide material to lower the resistance since because the source, drain and gate materials have relatively high resistance which may slow down the operation of the transistor..

IC Fabrication

Layout and Design Rules

The minimum feature size is L, the channel length of the MOSFET. Scalable rules (abstract dimensional unit , usually half of minimum feature size) The minimum feature size is L, the channel length of the MOSFET. MOSIS SCMOS http://www.mosis.org/Technical/Designrules/scmos/scmos-main.html#tech-codes http://www.mosis.org/Technical/Layermaps/lm-scmos_scna.html

In general, there are three main classes of design rule specifications In general, there are three main classes of design rule specifications. These are Minimum Width. Which is the smallest dimension permitted for any object in the layout drawing Spacing. Which is the smallest distance permitted between the edges of two objects. Surround. This apply to objects placed within larger objects (such as contacts). Every layer has minimum width and minimum spacing value, while surround are specified as required.

SCMOS Layout Rules - NWell

SCMOS Layout Rules - Active

SCMOS Layout Rules - Poly

SCMOS Layout Rules – Select

SCMOS Layout Rules - Contact to Poly & Contact to Active

SCMOS Layout Rules - Metal1

SCMOS Layout Rules - Via

SCMOS Layout Rules - Metal2

NMOS Layout

PMOS Layout

CMOS Inverter Circuit

STICK DIAGRAM Vdd = 5V   pMOS N MOS Vin

Stick Diagrams In Out V DD GND A Out V DD GND B Inverter NAND2

The steps to draw the layout of the CMOS inverter using L-EDIT SOFTWARE

* NODE NAME ALIASES * 1 = VSS (-10,-19.999) * 2 = VDD (-12.5,43.5) * 3 = VOUT (43.999,50.5) * 4 = VIN (23.499,51.5) Cpar1 1 0 C=6.36444f Cpar2 2 0 C=9.65448f Cpar3 3 0 C=9.51948f M4 3 4 2 2 PMOS L=0.6u W=3u AD=7.2p PD=10.8u AS=7.2p PS=10.8u M5 3 4 1 1 NMOS L=0.6u W=1.2u AD=3.96p PD=8.4u AS=3.96p PS=8.4u .END