DAQ Requirements M. Villa 21/02/2011

DAQ reading chain for L0-L5 HDI +Transition card+FEB+ROM DAQ chain independent on the chosen FE options Optical 1 Gbit/s Optical Link 2.5 Gbit/s ~50 cm FEB ROM LV1 High rad area 10Mrad/year Off detector low rad area Counting room Std electronics

FEB DAQ Constraints Handling of global signals Front-End specific: Clocks Lvl1 triggers Front-End specific: Chip configuration Clock, timestamp and trigger handling Hit collection (data push/pull) Monitoring: System check-up Chip calibration Large FPGA on board needed

Clock, Trigger handling Global clock at 50-60 MHz Time stamping every 70-120 ns (10 MHz) Maximum first trigger rate: 150 kH Variable time event window (approx 400 ns, detector specific) Minimal time between triggers: 70 ns. System synchronisation at few ns (<5 ns) level Only hits in trigger window have to be forwarded to ROM (DAQ next stage) Large FPGA on board needed

Data receiving Comunication on 1 Gbit/s optical links Bidirectional comunication to provide a path for Configuration Hit receiving and front-end checks. Selection or Preprocessing of hits needed Only hits in the trigger time window needs to be retained. Proper conversion of trigger signals for data-pull front-end chips Hit selection for data-push front-end chips

Final constraint on the Data shipping Comunication to ROM on 2.5 Gbit/s bidirectional link. Additional comunication line at large bandwidth (Gigabit ethernet?) for monitoring and calibration data receiving. An additional 2.5 Gbit/s link on board if we want to keep the SVT@trigger option open. Data push chips needed! Final constraint on the number of DAQ boards