ARM Cortex M3 & M4 Chapter 4 - Architecture RTLAB Wi Daehan
INDEX Operation modes and states Registers Special registers Floating point registers Behavior of the APSR (Application program status register) Memory system Exceptions & Interrupts SCB (System control block) Reset & Reset sequence
Operation modes and states
Registers R0 – R12 R13, stack pointer (SP) R14, link register (LR) R15, program counter (PC)
Special registers Program status registers MASK registers CONTROL register
Special registers Program status registers
Special registers Program status registers
Special registers MASK registers
Special registers CONTROL register
Floating point registers Single precision operation Define floating point operation behaviors Provide status information about operation results
Behavior of the APSR APSR contains status flags Integer operations (N-Z-C-V bits) Saturation arithmetic (Q bit) SIMD operations (GE bits)
Behavior of the APSR Integer status flags
Behavior of the APSR Q status flag
Behavior of the APSR GE bits
Memory system Memory system features 4GB linear address space Architecturally defined memory map Support for little endian and big endian memory systems Write buffer Memory Protection Unit (Optional) Unaligned transfer support
Memory system Memory map
Exceptions & Interrupts Various exception sources
Exceptions & Interrupts
Exceptions & Interrupts Nested vectored interrupt controller (NVIC) Flexible exception and interrupt management Nested exception/interrupt support Vectored exception/interrupt entry Interrupt masking
Exceptions & Interrupts Vector table
Exceptions & Interrupts Fault handling
SCB (System control block) Merged into the NVIC Controlling processor configurations (e.g., low power modes) Providing fault status information (fault status registers) Vector table relocation (VTOR)
Reset & Reset sequence Power on reset - reset everything in the microcontroller. System reset - reset just the processor and peripherals. Processor reset - reset the processor only.
Reset & Reset sequence
Reset & Reset sequence