Determinou o endereço de A

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Presentation transcript:

Determinou o endereço de A Ciclo 6 A Determinou o endereço de A 06 - add r1,r2,r3 05 - xor r11,r12,r13 04 - sub r8,r9,r10 03 - or r5,r6,r7 02 - and r2,r3,r4 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 7 A Determinou o endereço de A 07 - and r2,r3,r4 06 - add r1,r2,r3 05 - xor r11,r12,r13 04 - sub r8,r9,r10 03 - or r5,r6,r7 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 8 A Determinou o endereço de A 08 - or r5,r6,r7 07 - and r2,r3,r4 06 - add r1,r2,r3 05 - xor r11,r12,r13 04 - sub r8,r9,r10 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 9 A Determinou o endereço de A 09 - sub r8,r9,r10 08 - or r5,r6,r7 07 - and r2,r3,r4 06 - add r1,r2,r3 05 - xor r11,r12,r13 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 10 A Determinou o endereço de A 10 - xor r11,r12,r13 09 - sub r8,r9,r10 08 - or r5,r6,r7 07 - and r2,r3,r4 06 - add r1,r2,r3 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Ciclo 6 Com dependência de dados Determinou o endereço de A 06 - add r1,r2,r3 05 - xor r11,r12,r13 04 - sub r8,r9,r10 03 - or r5,r6,r7 02 - and r2,r3,r4 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 7 A Determinou o endereço de A 07 - and r2,r1,r4 06 - add r1,r2,r3 05 - xor r11,r12,r13 04 - sub r8,r9,r10 03 - or r5,r6,r7 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 8 A Determinou o endereço de A 08 - or r5,r6,r7 07 - and r2,r1,r4 06 - add r1,r2,r3 05 - xor r11,r12,r13 04 - sub r8,r9,r10 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 9 A Determinou o endereço de A 08 - or r5,r6,r7 07 - and r2,r1,r4 bolha 06 - add r1,r2,r3 05 - xor r11,r12,r13 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 10 A Determinou o endereço de A bolha bolha 08 - or r5,r6,r7 07 - and r2,r1,r4 06 - add r1,r2,r3 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 11 A Determinou o endereço de A bolha bolha bolha 08 - or r5,r6,r7 07 - and r2,r1,r4 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 12 A Determinou o endereço de A bolha bolha 09 - sub r8,r9,r10 08 - or r5,r6,r7 07 - and r2,r1,r4 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 13 A Determinou o endereço de A bolha 10 - xor r11,r12,r13 09 - sub r8,r9,r10 08 - or r5,r6,r7 07 - and r2,r3,r4 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Forwarding ID/EX EX/MEM MEM/WR mux Registers Data Memory mux mux NextPC mux Registers ALU Data Memory mux mux Immediate CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 6 Com forwarding A Determinou o endereço de A 06 - add r1,r2,r3 05 - xor r11,r12,r13 04 - sub r8,r9,r10 03 - or r5,r6,r7 02 - and r2,r3,r4 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r1,r7 Instr. 09 – sub r8,r1,r10 Instr. 10 – xor r11,r1,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 7 A Determinou o endereço de A 07 - and r2,r1,r4 06 - add r1,r2,r3 05 - xor r11,r12,r13 04 - sub r8,r9,r10 03 - or r5,r6,r7 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r1,r7 Instr. 09 – sub r8,r1,r10 Instr. 10 – xor r11,r1,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Vai ler o valor errado no fim do ciclo Determinou o endereço de A 08 - or r5,r1,r7 07 - and r2,r1,r4 06 - add r1,r2,r3 05 - xor r11,r12,r13 04 - sub r8,r9,r10 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r1,r7 Instr. 09 – sub r8,r1,r10 Instr. 10 – xor r11,r1,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

4 Ciclo 9 EX/MEM MEM/WB IF/ID ID/EX Address Reg File Memory ALU Memory Vai ler o valor errado no fim do ciclo Usa o valor correto via forwarding A Determinou o endereço de A 09 - sub r8,r1,r10 08 - or r5,r1,r7 07 - and r2,r1,r4 06 - add r1,r2,r3 05 - xor r11,r12,r13 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r1,r7 Instr. 09 – sub r8,r1,r10 Instr. 10 – xor r11,r1,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

4 Ciclo 10 EX/MEM MEM/WB IF/ID ID/EX Address Reg File Memory ALU Vai ler o valor certo no fim do ciclo Usa o valor correto via forwarding A Determinou o endereço de A 10 - xor r11,r1,r13 09 - sub r8,r1,r10 08 - or r5,r1,r7 07 - and r2,r1,r4 06 - add r1,r2,r3 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – add r1,r2,r3 Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r1,r7 Instr. 09 – sub r8,r1,r10 Instr. 10 – xor r11,r1,r13 Imm WB Data RD RD RD Registradores feitos com FFs tipo D acionados por nível CS252-s06, Lec 02-intro CS252 S05

Ciclo 8 Dependência verdadeira - LW Determinou o endereço de A 08 - or r5,r6,r7 07 - and r2,r1,r4 06 - lw r1,0(r3) 05 - xor r11,r12,r13 04 - sub r8,r9,r10 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – lw r1,0(r3) Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 9 A Determinou o endereço de A 08 - or r5,r6,r7 07 - and r2,r1,r4 bolha 06 - lw r1,0(r3) 05 - xor r11,r12,r13 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – lw r1,0(r3) Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 10 A Determinou o endereço de A 09 - sub r8,r1,r10 08 - or r5,r6,r7 07 - and r2,r1,r4 bolha 06 - lw r1,0(r3) Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – lw r1,0(r3) Instr. 07 – and r2,r1,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Ciclo 6 Desvios condicionais – bolhas para trás Determinou o endereço de A 06 - beqz r1, i10 05 - xor r11,r12,r13 04 - sub r8,r9,r10 03 - or r5,r6,r7 02 - and r2,r3,r4 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – beqz r1, i10 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 7 A Determinou o endereço de A 07 - and r2,r3,r4 06 - beqz r1, i10 05 - xor r11,r12,r13 04 - sub r8,r9,r10 03 - or r5,r6,r7 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – beqz r1, i10 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 8 A Determinou o endereço de A 08 - or r5,r6,r7 07 - and r2,r3,r4 06 - beqz r1, i10 05 - xor r11,r12,r13 04 - sub r8,r9,r10 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – beqz r1, i10 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Determinou o endereço de A Ciclo 9 A Determinou o endereço de A 10 - xor r11,r12,r13 08 - or r5,r6,r7 anulada 07 - and r2,r3,r4 anulada 06 - beqz r1, i10 05 - xor r11,r12,r13 Next PC IF/ID ID/EX MEM/WB EX/MEM MUX Next SEQ PC Next SEQ PC 4 Adder Zero? RS1 Reg File Address Memory MUX RS2 ALU Memory Data MUX MUX Sign Extend Instr. 01 – add r1,r2,r3 Instr. 02 – and r2,r3,r4 Instr. 03 – or r5,r6,r7 Instr. 04 – sub r8,r9,r10 Instr. 05 – xor r11,r12,r13 Instr. 06 – beqz r1, i10 Instr. 07 – and r2,r3,r4 Instr. 08 – or r5,r6,r7 Instr. 09 – sub r8,r9,r10 Instr. 10 – xor r11,r12,r13 Imm WB Data RD RD RD CS252-s06, Lec 02-intro CS252 S05

Pipeline melhorado 4 Instruction Fetch Instr. Decode Reg. Fetch Execute Addr. Calc Memory Access Write Back Next PC Next SEQ PC ID/EX EX/MEM MEM/WB MUX 4 Adder IF/ID Adder Zero? RS1 Address Reg File Memory RS2 ALU Memory Data MUX MUX Sign Extend Imm WB Data RD RD RD Perda de apenas um ciclo se o desvio for tomado CS252-s06, Lec 02-intro CS252 S05

Precise Exceptions in Static Pipelines Key observation: architected state only change in memory and register write stages. CS252 S05

Outra alternativa para reduzir o impacto dos desvios condicionais Predição de desvios! Mas, para compreender como implementar, precisamos saber como funcionam os caches! CS252-s06, Lec 02-intro CS252 S05