Comparison Study of Bulk and SOI CMOS Technologies based Rad-hard ADCs in Space Feitao Qi , Tao Liu , Hainan Liu , Chuanbin Zeng , Bo Li , Fazhan Zhao.

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Presentation transcript:

Comparison Study of Bulk and SOI CMOS Technologies based Rad-hard ADCs in Space Feitao Qi , Tao Liu , Hainan Liu , Chuanbin Zeng , Bo Li , Fazhan Zhao , Jiantou Gao , Gang Zhang , Jiajun Luo , Zhengsheng Han , and Zhongli Liu Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, CHINA Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences, Beijing 100029, CHINA AMICSA 2016-6-14

Overview INTRODUCTION SYSTEM ARCHITECTURE CIRCUITS DESIGN IMECAS INTRODUCTION SYSTEM ARCHITECTURE CIRCUITS DESIGN HARDENED APPROACHES EXPERIMENTAL RESULTS CONCLUSION AMICSA 2016-6-14

INTRODUCTION Harsh Space Environment: IMECAS Earth's radiation belts Cosmic rays Solar proton events AMICSA 2016-6-14

INTRODUCTION Rad-hard SOI CMOS V.S. Bulk CMOS : IMECAS higher speed (a)SOI CMOS (b) Bulk CMOS Rad-hard SOI CMOS V.S. Bulk CMOS : higher speed lower parasitic capacitance smaller short channel effects excellent capability of radiation hardness AMICSA 2016-6-14

INTRODUCTION RHBD & RHBP IMECAS Radiation Hardened by Design and Radiation Hardened by Process A 10bits 25Msps high reliability pipelined ADC as a prototype ADC 1992 Integrating analog to digital converter radiation hardness test technique and results 2006 Single-Event Sensitivity and Hardening of a Pipelined Analog-to-Digital Converter 2013 Radiation-Tolerant Code-Density Calibration of Nyquist-Rate Analog-to-Digital Converters transistor level comparison 2002 Comparison of the sensitivity to heavy ions of 0.25-μm bulk and SOI technologies Performance Comparison Between Bulk and SOI Junctionless Transistors 2014 Comparison of analog performance between SOI and Bulk pFinFET circuit level comparison This work Comparison Study of Bulk and SOI CMOS Technologies based Rad-hard ADCs in Space AMICSA 2016-6-14

INTRODUCTION IMECAS The bulk and SOI based CMOS ADC have identical schematic design and layout floor plan The bulk CMOS technology and radiation hardened SOI CMOS technology have identical technology node AMICSA 2016-6-14

SYSTEM ARCHITECTURE Sample and Hold Front-end 3+3+3+4 structure IMECAS Sample and Hold Front-end Extend the input bandwidth 3+3+3+4 structure 2.5bits/stage for first three stages 4bits/stage for last stage Digital Correction Logic Correct the error from comparators within the system redundancy AMICSA 2016-6-14

CIRCUITS DESIGN Sample and Hold Circuit IMECAS capacitor flip-around architecture lower power consumption better radiation hardness capability Larger feedback factor lower load capacitor bottom plate sampling and bootstrapped switch reduce the nonlinear effects of the switch charge injection clock feed through improve the input bandwidth AMICSA 2016-6-14

CIRCUITS DESIGN Sample and Hold Circuit Switched Capacitor Comparator IMECAS Sample and Hold Circuit gain-boosted folded cascade amplifier Effects of opamp caused by TID gain and bandwidth reduction DC offset increasing efficiently improve the gain without reducing the bandwidth Switched Capacitor Comparator Switched Capacitor Comparator with a preamplifier Low DC offset wide input common mode range AMICSA 2016-6-14

RADIATION HARDENED APPROACHES IMECAS Hardened System and Circuits for ADC prototype Properly determine and design system structure and circuits the 2.5bits/stage system structure the capacitor flip-around S/H the gain-boosted folded cascade amplifier the switched capacitor comparator with a preamplifier Properly increase the current and capacitor value in sensitive parts generates much smaller deviations when radiated deviations from comparators will be corrected by the digital error correction logic Hardened Layout for Bulk ADC Mitigate the sensitivity of Single event Latch-up Enough substrate contact around the transistor AMICSA 2016-6-14

RADIATION HARDENED APPROACHES IMECAS Radiation Hardened SOI CMOS Technology Single event Latch-up Immunity Join silicon dioxide on silicon substrate SEU and SEFI sensitivity mitigation Smaller charge collection volume Other Radiation Hardened Measures High level total ionizing dose radiation hardened AMICSA 2016-6-14

EXPERIMENTAL RESULTS Electrical Experiment IMECAS Table 1 Electrical Characteristics Comparison of SOI-based ADC and bulk CMOS ADC SOI ADC Bulk ADC FS(Hz) 25M Freq_vin(Hz) 2M Supply(V) 5 Consumption(mw) 240 DNL(LSB) ±0.4 INL(LSB) ±0.5 SNR(dB) 60.5 59.6 SFDR(dB) 72.3 74.4 SINAD(dB) 60.2 59.2 ENOB(bits) 9.7 9.5 (a)SOI CMOS ADC (b)Bulk CMOS ADC AMICSA 2016-6-14

EXPERIMENTAL RESULTS Electrical Experiment IMECAS SOI ADC exhibits better frequency characteristic smaller parasitic capacitance better I-V characteristic (a) SOI CMOS ADC (b) Bulk CMOS ADC AMICSA 2016-6-14

EXPERIMENTAL RESULTS TID Experiment Experiment conditions IMECAS TID Experiment Experiment conditions Radiation Cobalt-60 gamma radiation source at the room temperature static bias state dose rate of 50rad(Si)/s irradiated to 500krad(Si) Anneal 168 hours at 100℃ Measure point pre-radiation, 50k, 100k, 150k, 300k, 500krad(Si) and after anneal AMICSA 2016-6-14

EXPERIMENTAL RESULTS TID Experiment IMECAS SOI ADC TID tolerance > 300krad(Si) Bulk ADC TID tolerance <50krad(Si) AMICSA 2016-6-14

EXPERIMENTAL RESULTS SEE Experiment IMECAS DC analog input signals -0.8V, 0V and 0.8V At room temperature LET_Cl 17MeV•cm2/mg flux 104/cm2•s fluence 107/cm2 Noise window ±4LSB Expected Digital Output 96-103,504-511,920-927 AMICSA 2016-6-14

EXPERIMENTAL RESULTS SEE Experiment IMECAS SOI ADC SEL and SEFI immunity @LET = 63MeV·cm2/mg SEU cross-section 3.1X10-6cm2/device @LET = 17MeV·cm2/mg 9.6X10-6cm2/device @LET = 63MeV·cm2/mg Bulk ADC SEL and SEFI immunity @LET = 63MeV·cm2/mg single event upset (SEU) cross-section two order of magnitude higher than SOI ADC AMICSA 2016-6-14

CONCLUSION IMECAS In conclusion, by implementing simple RHBD approaches and taking the inherent advantage of the rad-hard SOI technology, the SOI-based ADC achieves the TID tolerance of 300krad(Si) at least, nearly one order of magnitude higher than bulk ADC, and the SEU cross-section of 9.6X10-6cm2/device at 63MeV·cm2/mg LET, lower than bulk ADC by two orders of magnitude, more suitable for harsh radiation environment applications. AMICSA 2016-6-14