OMEGA3 & COOP The New Pixel Detector of WA97 G. DARBO / INFN-GENOVA The New Pixel Detector of WA97 OMEGA3 : The 4 Operational Modes M0: Omega mode M1: The LHC test mode M2: Initialization of DelayAdjustRegisters M3: Initialization of Mask and Test flip-flop COOP : Basic Functionality Calibration voltage for OMEGA3 Precise Strobe calibration Automatic event R/O and zero suppression an OMEGA3 ladder and the external word Schedule and Plans AvailabilityConclusions G. Darbo - INFN / Genova LBL 6-11 Mar 1995

The New Pixel Detector of WA97

OMEGA3 / LHC1 Functionality The OMEGA3/LHC1 pixel size is 50x500 m 6 Flip-Flops in each OMEGA3 Pixel Cell: T: Test input Flip-Flop DL<2:0>: Delay Adjust register M: Output mask flip-flop D: output data flip-flop Prea    DL0 M D RS Th Coinc DL1 DL2 Trig. T Test Input Fast OR Interface with external word by a 16 bit data bus and... D<15:0>: Bidirectional Data Bus ...5 Control Lines: S<1:0>: Selects one of the four operation modes CS: Chip Select R/W: Read Write select line   D<15:0> S<1:0>,R/W CS0 CSn

OMEGA3 / LHC1 Functionality (cont.) 3 Timing Lines: STR: Strobe signal that latches the hit in the data flip-flop if it is in coincidence with the signal from the delay output; LV1: Level 1 trigger in LHC operation mode CLK: Clock Omega Mode Time Diagram 2s Ampl. Out Disc. Out Delay. Out Strobe LHC Mode Time Diagram Ampl. Out Disc. Out Delay. Out 2s LV1 Strobe 16 CLK

OMEGA3 / LHC1 Functionality (cont.) 2 Fast OR Lines FOE: Fast OR Output Enable FOO: Fast OR Output 1 Test Input Line TST: Test Input Pulse to all the amplifiers selected (T=‘1’) 1 Asynchronous Reset RST: S<1;0>=0: Reset all D Flip-Flops S<1:0>=1: Reset the FastOrDelay shift registers (LHC mode) S<1:0>=2: Reset DL<2:0> registers S<1:0>=3: Reset M and T flip-flops 6 Voltage For Parameter Compensation VTH: Discriminator Threshold VDL: Coarse Delay Set VDLA: Fine Delay Adjust VBIAS: Bias voltage for preamplifier VCOMP: Compensation for detector leakageVREF: Reference voltage for the previous ones 10 Power Pins

The 4 Operation Modes: MO (Omega Mode) No clock running during front-end event acquisition Column R/O of D flip-flops by 128 clock cycles Clock can be sent to columns with an ‘1’ at the corresponding Data line while the other can operate in normal way: Test of effect of clock cross-talk 2s Ampl. Out Disc. Out Delay. Out Strobe Omega Mode Time Diagram CLK Wait for Event Event R/O

The 4 Operation Modes: M1 (LHC Mode) Prea    DL0 M D Th Coinc DL1 DL2 Trig. T Fast OR 1 2 S1=0 S0=1 CS=0 15 CLK LV1 STR

The 4 Operation Modes: M2 & M3 Initialization Mode M2: Shift IN/OUT the DelayAdjust shift registers. 3x128 clock cycles to load the whole configuration. Destructive readout of loaded values for checking. Asynchronous reset by a RST with S1=1 & S0=0 Prea    DL0 M D Th Coinc DL1 DL2 Trig. T Fast OR Mode M3: Shift IN/OUT the Test and Mask flip-flops. 2x128 clock cycles to load the whole configuration. Destructive readout of loaded values for checking. Asynchronous reset by a RST with S1=1 & S0=1 Prea    DL0 M D Th Coinc DL1 DL2 Trig. T Fast OR

COOP Basic Functionality The COOP chip is aimed at the control of up to 6 OMEGA3 in a ladder The COOP has the basic functions of: Interface between the internal synchronous ladder bus and the external asynchronous bus Supplying 10 bias voltages to the OMEGA3: 6*VTH: Discriminator Threshold VDL: Coarse Delay Set VDLA: Fine Delay Adjust VBIAS: Bias voltage for preamplifier VCOMP: Compensation for detector leakageProvide fine adjust of strobe delay by ±100 ns with 6-bit resolution. Built in feature of both delay and width calibration for each of the 6 strobe outputs Fast readout, encoding and zero suppresion of pixel hits (a factor 20 speed up in a system configuration is espected) The COOP basic characteristics are: I/O pins: ~65 Digital 10 Analog ~10 Power CMOS, 1 m, 2 metal ES2 technology 35 40 mm2 die size

COOP Specs: Strobe Delays Strobe delays are generated by an active delay line and six 64-to-1 multiplexers. The six strobes can be individually adjusted to 3 ns with about 200 ns dinamic range. ~3 ns STR IN MUX 64 to 1 SEL (6-bits) STR1 STR6 STR IN STR 1 STR 6

COOP Specs: Strobe Delays Calibration Both strobe width and strobe delay can be measured by counting, for N input strobes: Number of clock edges in coincidence with the selected strobe output (STR 16) => this gives the average strobe width; Number pf clock edges in coincidence with the AND of the input strobe (STR-IN) and the negate of the selected strobe output (STR 16). Strobe width M U X STR-IN STR 1-6 M U X Strobe delay ZERO CNT DN CNT UP STOP CLK