Day 12: October 4, 2010 Layout and Area ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 12: October 4, 2010 Layout and Area Penn ESE370 Fall 2010 -- Townley (DeHon)

Today Layout Design rules Standard cells Transistors Gates 2 Penn ESE370 Fall 2010 -- Townley (DeHon) 2

Transistor Side view Perspective view 3 Penn ESE370 Fall 2010 -- Townley (DeHon) 3

Layout Sizing & positioning of transistors Designer controls W,L tox fixed Sometimes thick/thin oxide “flavors” 4 Penn ESE370 Fall 2010 -- Townley (DeHon) 4

NMOS Geometry L W Top view Perspective view 5 Penn ESE370 Fall 2010 -- Townley (DeHon) 5

NMOS Geometry L Color scheme Where is tox? S G D W Top view Red: gate Green: source and drain areas (n type) Where is tox? S G D W Top view 6 Penn ESE370 Fall 2010 -- Townley (DeHon) 6

tox Transistors built by depositing materials Constant rate of deposition (nm/min) Time controls tox Oxides across entire chip deposited at same time Same interval So, thickness is constant Process engineer sets value to maximize: Yield Performance 7 Penn ESE370 Fall 2010 -- Townley (DeHon) 7

NMOS vs PMOS Mostly talked about NMOS so far PMOS: “opposite” in some sense NMOS built on p substrate, PMOS built on n substrate Name refers to when channel is inverted Rabaey text, Fig 2.1 8 Penn ESE370 Fall 2010 -- Townley (DeHon) 8

PMOS Geometry L Color scheme NMOS built on p wafer S G D W n well Red: gate Orange: source and drain areas (p type) Green: n well NMOS built on p wafer Must add n material to build PMOS S G D W n well 9 Penn ESE370 Fall 2010 -- Townley (DeHon) 9

Body Contact “Fourth terminal” Needed to set voltage around device PMOS: Vb = Vdd NMOS: Vb = GND At right: PMOS (orange) with body contact (dark green) Side view: R.R. Harrison, ECE 5720 notes (Utah) 10 Penn ESE370 Fall 2010 -- Townley (DeHon) 10

Interconnect How to connect transistors Different layers of metal Intermediate layers “Contact” - metal to transistor “Via” - metal to metal Image from Rabaey text, pg48, Fig2-7k Rabaey text, Fig 2.7k 11 Penn ESE370 Fall 2010 -- Townley (DeHon) 11

Interconnect Cross Section Image from Rabaey text, pg48, Fig2-7k ITRS 2007 12 Penn ESE370 Fall 2010 -- Townley (DeHon) 12

Masks Define areas want to see in layer Think of “stencil” for material deposition Use photoresist (PR) to form the “stencil” Expose PR through mask PR dissolves in exposed area Material is deposited Only “sticks” in area w/ dissolved PR 13 Penn ESE370 Fall 2010 -- Townley (DeHon) 13

Masking Process Goal: draw a shape on the substrate Silicon wafer Goal: draw a shape on the substrate Simplest example: draw a rectangle 14 Penn ESE370 Fall 2010 -- Townley (DeHon) 14

Masking Process First: deposit photoresist Silicon wafer Mask 15 Penn ESE370 Fall 2010 -- Townley (DeHon) 15

Masking Process Expose through mask UV light 16 Penn ESE370 Fall 2010 -- Townley (DeHon) 16

Masking Process Remove mask and develop PR Exposed area dissolves This is “positive photoresist” Negative photoresist? 17 Penn ESE370 Fall 2010 -- Townley (DeHon) 17

Masking Process Deposit metal through PR window Why not just use mask? Then dissolve remaining PR Why not just use mask? Masks are expensive Shine light through mask to etch PR Can reuse mask 18 Penn ESE370 Fall 2010 -- Townley (DeHon) 18

Logic Gates How to build? Connect NMOS, PMOS using metal HW4, part 6: reverse engineer layouts into gates 19 Penn ESE370 Fall 2010 -- Townley (DeHon) 19

Inverter Layout Example 20 Penn ESE370 Fall 2010 -- Townley (DeHon) 20

Inverter Layout Example Start with PMOS, NMOS transistors Space for interconnect 21 Penn ESE370 Fall 2010 -- Townley (DeHon) 21

Inverter Layout Example 22 Penn ESE370 Fall 2010 -- Townley (DeHon) 22

Inverter Layout Example Add body contacts Connect gates of transistors 23 Penn ESE370 Fall 2010 -- Townley (DeHon) 23

Inverter Layout Example 24 Penn ESE370 Fall 2010 -- Townley (DeHon) 24

Inverter Layout Example Add contacts to source, drain, gate, body Connect using metal (blue) 25 Penn ESE370 Fall 2010 -- Townley (DeHon) 25

Design Rules Why not adjacent transistors? Plenty of empty space If area is money, pack in as much as possible Recall: processing imprecise Margin of error for process variation 26 Penn ESE370 Fall 2010 -- Townley (DeHon) 26

Design Rules Contract between process engineer & designer Minimum width/spacing Can be (often are) process specific Lambda rules: scalable design rules In terms of  = 0.5 Lmin Can migrate designs from similar process Limited scope: 45nm process != 1m 27 Penn ESE370 Fall 2010 -- Townley (DeHon) 27

Design Rules: Some Examples 3 2  2 1.5 2 6 n doping p doping gate contact metal 1 metal 2 via Legend Penn ESE370 Fall 2010 -- Townley (DeHon)

Layout Revisited How to “decode” circuit from layout? 29 Penn ESE370 Fall 2010 -- Townley (DeHon) 29

Layout to Circuit 1. Identify transistors 30 Penn ESE370 Fall2010 -- DeHon Penn ESE370 Fall 2010 -- Townley (DeHon) 30

Layout to Circuit 2. Add wires 31 Penn ESE370 Fall 2010 -- Townley (DeHon) 31

Layout to Circuit 2. Add wires 32 Penn ESE370 Fall 2010 -- Townley (DeHon) 32

Layout to Circuit 2. Add wires 33 Penn ESE370 Fall 2010 -- Townley (DeHon) 33

Layout to Circuit 2. Add wires 34 Penn ESE370 Fall 2010 -- Townley (DeHon) 34

Layout #2 (practice) 35 Penn ESE370 Fall 2010 -- Townley (DeHon) 35

Standard Cells Lay out gates so that heights match Rows of adjacent cells Standardized sizes Motivation: automated place and route EDA tools convert HDL to layout 36 Penn ESE370 Fall 2010 -- Townley (DeHon) 36

Standard Cell Area inv nand3 All cells uniform height Width of channel determined by routing Cell area Identify the full custom and standard cell regions on 386DX die http://microscope.fsu.edu/chipshots/intel/386dxlarge.html Penn ESE370 Fall 2010 -- Townley (DeHon)

Admin HW4 – slight update online to clarify Q1 HW3 – trickier than intended in places Our guess is 1, 2, maybe 7 (let us know if that’s not where) Office hours to clear up any remaining confusion? Andre back for Wed. Lecture Penn ESE370 Fall 2010 -- Townley (DeHon)

Big Idea Layouts are physical realization of circuit Geometry tradeoff Can decrease spacing at the cost of yield Design rules Can go from circuit to layout or layout to circuit by inspection 39 Penn ESE370 Fall 2010 -- Townley (DeHon) 39