Future trends in nano-CMOS cell design with Microwind Etienne.sicard@insa-toulouse.fr

Toulouse, France Route: 9.350 km Distance: 7.200 km Pune, India WHERE I COME FROM Toulouse, France Route: 9.350 km Distance: 7.200 km Pune, India

Founded in -120 B.C (heavy history) TOULOUSE, FRANCE Founded in -120 B.C (heavy history) Best place to study in France (2015 ranking) (heavy responsibility) Airbus A380 (heavy airplane) Cassoulet (heavy food) Rugby (heavy efforts)

CONTENTS General trends Technology Trends About Microwind FinFET implementation Design for manufacturability The educational dilemma Link to Research Conclusion

1 GENERAL TRENDS

INDUSTRY CURRENT CHANGES Meeting the Industrial 4.0 challenge : cyber-physics systems Productivity, Efficiency, Safety, Connectivity

Electronic Market Growth Share of system sales 2020 vs 2015 VISION 2020 Increasing disposable income, Expanding urban population, Growing internet penetration and Availability of strong distribution network Smartphones Internet of Things PC TV Automotive Tablets Game consoles Medical Servers -10% Growth 10% 20% Electronic Market Growth

Year THE ELECTRONIC MARKET GROWTH Market Growth Individuals 30% Companies HDTV 3G 4G IoT ADAS PC at home Internet GSM MP3 DVD Flat screens Automotive Society 20% PC in companies Audio CD Defense Local Energy Security Medical 3% 2014 4% 2017 10% Recession Bank crash 2% 2013 3% 2015 Recession -10% Telecom crash 83 86 89 92 95 98 01 04 07 10 13 16 Year Adapted from Electronique International Mai 21, 2009

4G Technology 130nm 90nm 45nm 28nm 14nm 5nm Complexity 100M 250M 500M We are here 4G Technology 130nm 90nm 45nm 28nm 14nm 5nm Complexity 100M 250M 500M 2G 7G 150 G Packaging Mobile generation 4G 4G+ 5G 3G 3G+ 2004 2007 2010 2013 2016 2020 Core+ DSP 1 Mb Mem Core DSPs 10 Mb Mem Dual core Dual DSP RF Graphic Process. 100 Mb Mem Sensors Quad Core Quad DSP 3D Image Proc Crypto processor Reconf FPGA, Multi RF 1 Gb Memories Multi-sensors ? Embedded blocks

4G 3G 2G 4G BUSINESS http://www.ericsson.com/ericsson-mobility-report We are here 7.8 billion 4G 3G 2G http://www.ericsson.com/ericsson-mobility-report

INTERNET OF THINGS

TOWARDS AUTOMATIC DRIVE ADAS TOWARDS AUTOMATIC DRIVE 2020 : Injury-free driving 2030: Accident-free driving ? 2040: Autonomous driving?

2 TECHNOLOGY TRENDS

TOWARDS 10GT 8-bit 10 GT in 2015 1 GT in 2010 Multi-core Quadcore Dual core Quadcore 1 GT in 2010

MOS CURRENT DRIVE We are here MOS Current drive (mA/µm) 2.0 1.5 1.0 FinFET for increasing drive current and reducing leakage High K Metal Gate to increase field effect We are here MOS Current drive (mA/µm) Strain to increase mobility High performance 2.0 General Purpose 1.5 Ioff: 100nA/µm Low power 1.0 10nA 1 nA 0.5 0.0 130 nm 90 nm 65 nm 45 nm 32 nm 20 nm 14 nm 10 nm Intrinsic performances Gate material Technology node Strain

Data Rate per pin (Gb/s) CURRENT CHANGES Technology Faster and faster memory DDR4, LPDDR is on the market DDR5, LPDDR5 is under development DDR4: 250ps 2010 Laptop Memory 2012 2014 2016 2018 2020 Data Rate per pin (Gb/s) DDR3 DDR2 1 Gb/s 10 Gb/s 100 Gb/s WideIO LPDDR2 LPDDR3 DDR4 LPDDR1 Mobile Memory WideIO2 LPDDR4 DDR5 We are Here 3D 2D

SUPPLY VOLTAGE SCALE DOWN The supply is lowered below 1V 14-nm technology Supply (V) 5.0 0.8 V inside, 1.2V outside 3.3 I/O supply 2.5 Core supply 1.8 1.2 1.0 0.35µ 0.18µ 130n 90n 65n 45n 32n 20n 14n 10n 7n Technology node

Technology CURRENT CHANGES 2.5D high bandwidth and high density DRAM with TSV and Si Interposer 1 tera-bit/cm2 achieved 5 years ahead from roadmaps We are Here

65nm 28nm 14nm Power -50% -80% 65nm 28nm 14nm SCALE DOWN BENEFITS Smaller Faster Less power consumption Cheaper (if you fabricate millions) 65nm 28nm 14nm Power -50% -80% 65nm 28nm 14nm

SCALE DOWN BENEFITS Maximum die size One Core One core AMD dual core 65nm Intel Octa core 22nm 8 cores instead of 1 using the same space 3 times faster 10 times less power consumption

REASONS OF COST EXPLOSION TECHNOLOGY INNOVATION & COST REASONS OF COST EXPLOSION Performance improvements Strain eSiGe, High-K dielectric Metal gate Low-K inter dielectrics, FinFET New options Local interconnects New constraints double patterning, FinFET

TECHNOLOGY TRENDS TOWARDS BILLION $ FAB

TECHNOLOGY INNOVATION & COST Less and less companies in the 14-nm market Keynote_Ajit Manocha_GLOBALFOUNDRIES

Embedded SiGe (e-SiGe) Improved p mobility High K gate dielectric TECHNOLOGY INNOVATION & COST Main target Type of innovation First order effect Device performance Strain Improved n mobility Embedded SiGe (e-SiGe) Improved p mobility High K gate dielectric Increased field effect Metal gate Decreased leakage FinFET Higher current density Interconnect performance Low K inter dielectrics Reduced crosstalk and delay Local interconnect Higher density Manufacturability Double patterning Improved yield

ROADMAP ACCORDING TO TSMC Research at TSMC Description Schedule 10nm logic platform technology and applications 3rd generation FinFET CMOS platform technology for System-on-chips (SoC) 2016 7nm logic platform technology and applications 4th generation FinFET CMOS platform technology for System-on-chips 2017 3D IC Cost-effective solution with better form factor and performance for System-in-package (SiP) 2016 ~ 2017 Next-generation lithography EUV and multiple e-beam to extend Moore’s Law 2016 ~ 2019 Long-term research SoC technology and transistors for 5nm node and beyond 2015 ~ 2019 http://www.tsmc.com/english/dedicatedFoundry/technology/future_rd.htm

Processor die GOING 3D THERE IS PLENTY OF SPACE ON THE TOP 3D technology uses stacked dies, through-silicon-vias Enables 10-20 Gb/s/pin at 1.0V Samsung 3D (Galaxy 6) vs PoP (Galaxy 5) : 30% faster 20% less power Less heat Thinned memory die 10 µm Multicore 350 µm thickness Direct bond interconnect (DBI) Package leadframe (GND) Through Silicon Via (TSV) Possible 3rd die Bottom die Upper die http://www.youtube.com/watch?v=Rw9fpsigCfk

3 ABOUT MICROWIND

www.microwind.org WHAT IS MICROWIND Microwind is a unique educational tool for designing nano-CMOS cells Microwind may be configured in any technology from 1.2µm downto 14nm Microwind illustrates 2D, 3D aspects of Ics Microwind simulates cells & blocks using embedded simulator www.microwind.org

Acceptable for simulators MOS MODELS Microwind uses Level1, Level3, and a simplified version of BSIM4, adapted to FinFET “Typically, FinFET models have over 1,000 parameters per transistor, and more than 20,000 lines of C code” BSIM in Microwind uses 25 parameters and 250 lines of code… but makes many simplifications Bsim CMG Bsim6 Acceptable for simulators 1000 Bsim4 Bsim3 Bsim2 Bsim Model parameters 100 MM9 Level 2 Level 3 Acceptable for teachers 10 Level 1 Acceptable for students 1 1970 1980 1990 2000 2010 2020 Year

2006 – New Delhi 2006 – Pune www.microwind.org WHAT IS MICROWIND Books on CMOS basic & advanced design have been written by E. Sicard, S. Ben Dhia and published by Tata-McGrawHill in 2006 Microwind has been successfully deployed in India and in some universities around the world by ni2designs 2006 – Pune www.microwind.org

MICROWIND FEATURES FOLLOWING THE SCALE DOWN 2 supply Low K Double patterning Metal gate nMOS Strain Pocket implant pMOS Strain High K oxide 8 Metal Double gates

2nd generation strain, 10 metal layers 32/28nm 2010 High-K metal gate NANO-CMOS APPLICATION NOTES Technology node   Year of introduction Key Innovations 90nm 2003 SOI substrate 65nm 2004 Strain silicon 45nm 2008 2nd generation strain, 10 metal layers 32/28nm 2010 High-K metal gate 20nm 2013 Replacement metal gate, Double patterning, 12 metal layers 14nm 2016 FinFET www.microwind.org > Application Notes

MICROWIND LAMBDA-BASED DESIGN Gate pitch Microwind works in lambda units (λ) Not optimum layout but independent of technology Design rules have remained nearly the same for 20 years λ is nearly half of technology (8nm in 14-nm node) Channel length is 2 λ Minimum gate pitch is 8 λ (2+6) Minimum metal pitch is 6 λ (3+3) Channel length Metal pitch

2500 1000 design rules DESIGN RULES Microwind DRC only checks around 100 basic design rules In 14-nm technology, more than 2500 design rules have been listed in the design kit Layouts cannot be fabricated without full DRC 130nm 500 design rules 65nm 1000 design rules 14nm 2500

4 FINFET IMPLEMENTATION

MICROWIND FINFET Microwind’s FinFET implementation based on a selection of 10 scientific publications The FinFET is used starting 14-nm node Layout, size and performances inspired from “average” 14-nm FinFET Scaling to 10-nm & 7-nm nodes Application note in progress Standard cell level parasitics assessment in 20nm BPL and 14nm BFF P. Schuddinck, IEDM 2012 3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits Ajay N. Bhoj, IEEE VLSI, Vol 21, N°11, 2013

The FinFET device has a different layout style than the MOS device FROM MOSFET TO FINFET >= 20nm <= 14nm The FinFET device has a different layout style than the MOS device Instead of a continuous channel, the FinFET uses fins FinFET provides the same Ion current at a smaller size FinFET provides lower leakage current Ioff at the same Ion fins

New screen in Microwind INTRODUCING THE FINFET MOS Parameter Typical value Width (W) 6 - 12 λ Length (L) 2 λ New screen in Microwind FinFET Parameter Typical value Number of fins (NF) 2 - 5 Fin pitch (PF) 6 λ Fin thickness (TF) 1 λ Fin length or gate length (LG) 2 λ

3D OF FINFET USING MICROWIND Microwind enables a 3D view of the FinFET P-FinFET Fin 4 Drain Fin 3 Fin length (LG) Fin 2 Fin thickness (TF) Source Fin 1 Fin height (HF) Gate N-FinFET

FIN from Drain to Source Total equivalent channel width Weq FIN BENEFITS Fin thickness (TFIN) The total equivalent channel width is higher in FinFET than in MOSFET Weq = 2*HFIN+TFIN Benefit around 30% in current drive Gate Fin height (HFIN) FIN from Drain to Source Total equivalent channel width Weq MOS Fin Ioff Patton, Evolution and Expansion of SOI in VLSI Technologies: Planar to 3D, IEEE International SOI Conference 2012 Ion

GENERATING A FINFET Fin Length, equal to gate length, (LG) is 2 lambda (16 nm) by default Fin thickness (TF) is set to 1 lambda (8 nm) Fin pitch (PF) is set to 6 lambda (48nm) Number of fingers (NFIN) range from 1 to 4 usually FinFET comme with dummy gates for manufacturability

GENERATING A FINFET HD: High density drawing style : 2 fins HP : High performance drawing style : 4 fins 1 fin exists in very high density cells such as SRAM FinFET with more than 4 fins drive string currents

FINFET EXAMPLE Hand-made FinFET inverter 2-fin strategy for high density Dummy poly gates on both sides for manufacturability

5 DESIGN FOR MANUFACTURABILITY

Ion Ion Ioff Ioff FINFET MANUFACTURABILITY Fins should be aligned and horizontal, regular pitch 6  (1+5) Non-aligned fins may lead to gate distortion and current performance spread Ion Ion Ioff Ioff

FINFET MANUFACTURABILITY Gates should be aligned and vertical, regular pitch with 8  minimum (2+6)

With 2 fins, Weff=140nm FINFET MODEL BSIM4 is a good model for MOS devices BSIM-CMG is targetted to FinFET, but corresponds to a completly new model The HFIN and TFIN parameters have been added to BSIM4 in Microwind to handle the FinFET HFIN: Fin Height TFIN: Fin thickness Fin thickness (TF) 10nm With 2 fins, Weff=140nm Fin height (HF) 30nm

Main target Pitch  nm Used for M7, M8 4 24 192 Supply M5, M6 3 18 144 INTERCONNECTS Metal stack Main target Pitch  nm Used for M7, M8 4 24 192 Supply M5, M6 3 18 144 Long routing M3, M4 2 12 96 Medium routing M1, M2 1.4 8 64 Short routing Gate, Local interc. 1 6 48 Intra-cell routing

Nearly manufacturable Not manufacturable STUDENT DESIGNS Nearly manufacturable Not manufacturable ALU project by Master students INSA, 2016 SRAM project by Master students INSA, 2016

6 THE EDUCATIONAL DILEMMA

The commercial chip design tools available today are very powerful TEACHING NANO-CMOS Physics CMOS design Teaching hours System integration Years Embedded software The commercial chip design tools available today are very powerful However, these tools are highly complex and need long time to learn. Teaching hours in Nano-CMOS are decreased Physics of semiconductors is exploding in complexity (100-1000 parameters in MOS models) Student and engineer diversity must be considered. Gaps in the background knowledge must be addressed EDUCATIONAL NEEDS

AUDIENCE AND LEARNING CURVE Tools are used by large number of students at undergraduate level Design tools should provide intuitive design, simulation and visualization environments Design tools should be easily accessible. Most of the work is done out of regular teaching hours (e-learning, project-based..) Target course and practical training duration: 15 H Professional tools Graduates Undergraduates PhDs Educational Short sessions : Simple design Concepts Long practical Ambitious designs L arge number of students Reduced number of students Learning curve Hours Industry - oriented tools Education oriented tools Rapid progress 5 10 15 20 S low EDUCATIONAL NEEDS

Technology scale down, where we come from, where we are, where we go.. WHAT I DO AT INSA Technology scale down, where we come from, where we are, where we go.. A tutorial on MOS devices, based on problem-based learning The design of inverters, and a simple ring oscillator, and a small student contest. The design of basic logic gates introducing interconnect design, compact design strategies, impact on switching speed and power consumption. The design of analog blocs amplification, voltage reference, addition of analog signals, and mixed-signal blocs A small project, e.g. converter, processing unit, OpAmp, radio-frequency block, etc.. MICROWIND

Try to optimize the VCO for highest possible speed BASIC GATE DESIGN TYPICAL SCENARIO Design of MOS Design of inverters Design of a VCO Try to optimize the VCO for highest possible speed Improve MOS size Change MOS options Make the layout more compact Keep an eye on power consumption 2. 1. 4. 3. MICROWIND

ENGAGE STUDENTS IN A STIMULATING LEARNING EXPERIENCE PROJECT EXAMPLES 2. 1. ENGAGE STUDENTS IN A STIMULATING LEARNING EXPERIENCE Circuit analysis and optimization using WinSpice Combinational and sequential circuit layouts ALU Design Power amplifier Bluetooth 3. 4. MICROWIND

EVALUATION EVALUATION The CMOS design course is evaluated regularly the students Course evaluation questionnaire containing ten core questions and open text response. The students usually rate the course very highly in all the evaluation items. The course was in the in the top-5 courses offered in engineering in UniSA, Australia (Dr. Aziz). Regular positive feedback from colleagues # Question 1 I have a clear idea of what is expected of me in this course. 2 The ways in which I was taught provided me with opportunities to pursue my own learning. 3 The course enabled me to develop and/or strengthen a number of the qualities of a [University of South Australia,INSA] graduate. 4 I felt there was a genuine interest in my learning needs and progress. 5 The course developed my understanding of concepts and principles 6 The workload for this course was reasonable given my other study commitments 7 I have received feedback that is constructive and helpful. 8 The assessment tasks were related to the qualities of a [University of South Australia, INSA] graduate. 9 The staff teaching in this course showed a genuine interest in their teaching. 1 0 Overall I was satisfied with the quality of this course EVALUATION

John Uyemura, Professor, Georgia Tech COMMENTS "I have been learning the Microwind program, and are having a fun time-it is an excellent piece of work! I have decided that I would like to also write a book using the program. I would encourage you two to complete the writing on the book as I think that it will receive a warm reception.” John Uyemura, Professor, Georgia Tech “Microwind Inside” EDUCATIONAL NEEDS

COMMENTS “From just a few logic gates, we have created a 4-stage binary counter and compiled it into layout…” “The 24-hours clock project was a good exercise which permitted us to see how it is inside a semiconductor and how it works.” “We learned a lot about designing integrated circuit. We faced some practical problems, and tried to solve them or to understand them.” “This study allows us to understand the DAC running. In spite of some design problems, we managed to make the DAC work well.” “Before doing this project, we hadn’t thought that there are as many ways to realize an amplifier. It’s an area not easy to understand. Each technique has its limit. We tried to optimize our operational amplifier design to maximize the gain “The tools offer easy to use menus for design and simulation, and the choice of a range of technology models to enable students to develop critical design and analysis skills using the latest technologies.” (Malaysia). “Microwind and Dsch tools are used for VLSI teaching programs at both postgraduate and undergraduate levels. The project-based methodology supported by a variety of learning resources has made the learning of VLSI Design very stimulating.” (Bangladesh). “Exploring the tools is a lot of fun. The interface is very friendly, and the program is both educational and useful for designing CMOS chips.” (USA) EVALUATION

STUDENT REPORTS The best student reports are put on-line on www.microwind.org > Student reports Student works from other institutes and countries are also placed on-line

www.microwind.net, www.microwind.org 1,000,000 PAGE VIEWS 700,000 page vues in microwind commercial site 300,000 page vues in microwind documentation site 150 documentation & app. Note downloads/week Sites www.microwind.net, www.microwind.org

EVALUATION FUTURE TRENDS IN NANO-CMOS Teach FinFET Teach fast IOs 5G mobile phones will use 10-nm & 7-nm FinFET in 2020 Multi Gbit IOs will link processors and memories 3D-ICs will be used in many high-end applications IoT for smart, low cost, low power applications putting together RF, networking, processors and sensors Teach FinFET Teach fast IOs Teach 3D-ICs Teach IoT design EVALUATION

7 LINK TO RESEARCH

The Biomi2 project IC-EMC MICROWIND AS A RESEARCH TOOL Microwind & DSCH have been used as platforms for PhD studies at INSA Chen Xi developed DSCH for designing a logic IC for medical application (2000) Sonia Ben Dhia studied and measured crosstalk in ICs (2005) Alexandre Boyer developed several tools for Electro-Magnetic Compatibility (EMC) in DSCH derivative “IC-EMC” (2008) The Biomi2 project IC-EMC

RESEARCH WITH MICROWIND Microwind used and cited in 450+ papers & publications 2011 A CMOS VLSI implementation of Mean Life Time(MLT) Detector for Bio-luminescence Sensor 4-Bit Fast Adder Design Topology and Layout with Self-Resetting Logic for Low Power VLSI Circuits AREA EFFICIENT 3.3GHZ PHASE LOCKED LOOP WITH FOUR MULTIPLE OUTPUT USING 45NM VLSI TECHNOLOGY Flip-Flop Circuit Families:Comparison of Layout and Topology for Low Power VLSI Circuits Low-Area Low-Power and High-Speed TCAMS POWER EFFICIENT DESIGN OF COUNTER ON .12 MICRON TECHNOLOGY Design and Performance Analysis of 5 GHz CMOS RF Front-End Circuits for IEEE 802.11 a Application DESIGN AND DEVELOPMENT OF ANALOG TO DIGITAL CONVERTER USING DIFFERENTIAL RING OSCILLATOR Design and test challenges in Nano-scale analog and mixed CMOS technology Layout Design of a 2-bit Binary Parallel Ripple Carry Adder Using CMOS NAND Gates with Microwind A NOVEL DESIGN FOR HIGHLY COMPACT LOW POWER AREA EFFICIENT 1-BIT FULL ADDERS Area, Delay and Power Comparison of Adder Topologies Comparative Analysis of 7T and 6T SRAM Using 0.18μm Technology COMPARATIVE ANALYSIS OF ENERGY-EFFICIENT LOW POWER 1-BIT FULL ADDERS AT 120NM TECHNOLOGY 2012 Comparative Analysis of Low Power 4-bit Multipliers Using 120nm CMOS Technology COMPARISON AMONG DIFFERENT CMOS INVERTER WITH STACK KEEPER APPROACH IN VLSI DESIGN Comparison of Transistor count Optimized Full adders with modified CMOS Full adders Design and Analysis of Low Power Full Adder Using Adiabatic Technique Design and Performance of CMOS Circuits in MICROWIND Design of a Low Power Flip-Flop Using MTCMOS Technique Design of a Multiplexer In Multiple Logic Styles for Low Power VLSI Designing and Analysis of 8 Bit SRAM Cell with Low Subthreshold Leakage Power Implementation of LFSR Counter using CMOS Chip Technology Leakage Power Reduction in CMOS VLSI Circuits Novel keeper technique for Domino logic circuits in DSM Technology Ultra Wideband Low Noise Power Amplifier Low Power 8T Column Decoupled Sram Cell with Bit Line Decoupled Current Mode Sense Amplifier Interconnect Analysis of a Novel Multiplexer Based Full-Adder Cell for Power and Propagation Delay Optimizations Journals and Conferences International Journal of Engineering Science and Technology IEEE Int’l Conf. on Computer & Communication Technology IEEE International Conference on Recent Trends in Information, Telecommunication and Computing IEEE Trans Education International Conference on Electrical and Computer Engineering ICECE International Journal of VLSI design & Communication Systems International Journal of Engineering Research and Applications International Journal of Computer Applications International Journal of Soft Computing and Engineering European Journal of Scientific Research World Journal of Science and Technology International Journal of Advances in Engineering & Technology International Journal of Emerging Technology and Advanced Engineering International Conference on Emerging Frontiers in Technology for Rural Area Microelectronics Journal International Journal of Modern Engineering Research World Academy of Science, Engineering and Technology APPLICATION NOTES

SCIENTIFIC PUBLICATIONS In July 2016, around 470 scientific publications using of making reference to Microwind

CONCLUSION

CONCLUSION The electronic market growth should be driven by 5G mobile, automatic drive, Internet of Things, etc. The trends towards 7nm technology have been described Microwind is a unique educational tool in nano-CMOS design, with scalability to 7nm FinFET is a major change in gate design Manufacturability limits the design space Impressive number of publications with reference to Microwind Future: 3D ICs, 100Gb/s, 5G communications

Thank you for your attention Etienne.sicard@insa-toulouse.fr