USB 3.1 Gen1 Testing with the RTO Oscilloscope Guido Schulze, Product Manager 1TDP Rev. 1.0, 14. August 2017

Outline USB Market trends & Technology overview USB 3.1 Gen1 Trigger & Decode option Signal Integrity Debugging Examples 03-17 Oscilloscope Training - USB, PCIe interface options

Market trends - USB More data: All industries are impacted USB 3.1 Specification Flexible Power: Power supply and charging USB-PD Specification Unified Connector: Applicable beyond USB USB Type C Specification 03-17 Oscilloscope Training - USB, PCIe interface options

Market Trend: USB and it’s progress 1.5 Mbps Low Speed USB1.1 12 Mbps Full Speed USB2.0 480 Mbps High Speed USB3.0 5 Gbps USB3.1 Gen1 5 Gbps Super Speed USB3.1 Gen2 10 Gbps Super Speed+ USB Type-C™ 1996 1998 2000 2008 2013 2005 2010 2011 2015 Wireless USB rev1.0 rev1.1 USB On-The-Go USB Power Delivery 03-17 Oscilloscope Training - USB, PCIe interface options

Market Trend USB Increasing Serial Data Bandwidth USB 2.0, 480 Mb/s (2000) Shift from slower, wide, parallel buses to narrow, high speed serial bus 40x faster data rate, support for new connectors & charging USB 3.0, 5 Gb/s (2008) ~10x faster data rate over 3 meter cable Faster edges, ‘closed eye’ architecture USB 3.1, 5 Gb/s (Gen1)/10 Gb/s (Gen2) (2013) 2x faster data rate over 1 meter cable ‘Scaled’ SuperSpeed / SuperSpeed+ implementation High Speed USB Cable SuperSpeed USB Cable 03-17 Oscilloscope Training - USB, PCIe interface options Let’s briefly look at the history of USB and where we’ve come from. It’s been well over ten years since high speed USB was introduced. This was quite an improvement over the previous peripheral i/o standards available at the time. Not only did USB2 have a faster transfer rate but also provided a much improved user experience with its plug and play style operation. Eventually though USB2 didn’t quite have enough horsepower for some of the more demanding applications like HD video or interfacing with larger data storage. For many tasks like synchronizing large files with an external drive USB 5 Gb/s may seem good enough. Interestingly though as we project out in the future as to where the I/O bottleneck is it is moving away from the storage or display products now back to the interconnect. At 5 Gb/s bit rate for example the effective transfer rate will saturate some of the newer SSDs that have transfer rates of 500 Mbytes per sec or more. Then if you want to connect multiple drives or add in an HD monitor the per port bandwidth drops even more. The USB 3.1 10 Gb/s rate should give us some head room for the future.

Technologie Overview USB 3.1 03-17 Oscilloscope Training - USB, PCIe interface options

USB Ecosystem Devices Hosts Hubs A to mB HDDs Thumbdrives A to Std B Tablets Hubs Goal USB.org: Any certified host works with any certified hub or device. Video Adapters 03-17 Oscilloscope Training - USB, PCIe interface options

Evolution of the USB3 Connector Standard A Plug (2008) ~5000 insertions 900mA Micro B Plug (2008) ~10,000 insertions 900mA USB Type-C Plug (2015) ~10,000 insertions 5A* Reversible Orientation 03-17 Oscilloscope Training - USB, PCIe interface options A lot of what’s been possible in terms of bandwidth capability for USB was done through a well designed interconnect. Let’s take a quick look at the evolution of the USB connector. The standard USB type A is probably the most universally recognized connector on the market today. The USB3 spec not only increased the current sourcing capabilities but also shrank the connector size to a micro form factor. This was to accommodate the growing number of small form factor designs like tablets and mobile phones. With the introduction of the type C connector it’s clear the game has changed and in so many ways. This connector will lead the way to much better user experiences. There was a lot of consideration put into every aspect of typical usage models from mechanical robustness, current sourcing, scalable bandwidth, host or device role swapping, and even supporting other signaling or “alternate modes” as it’s referred to in the spec. My favorite by far is the reversible orientation that allows a plug to connect to a device or host in any direction. Let’s take a look closer look at the connector.

USB 3.1 Gen1 Overview (I) 5 Gb/s SuperSpeed operation Clocks Unidirectional TX and RX 8b10b coding Data scrambling Clocks Separate clock sources for host & device Spread spectrum clock Support for cables with up to 7.5dB of loss Practical limit is 3 m length (with AWG28 wire) Backward compatibility with USB 2.0. Legacy signals are physically & electrically isolated from SuperSpeed signals. SuperSpeed products must also complete USB 2.0 compliance testing for logo certification. 03-17 Oscilloscope Training - USB, PCIe interface options

USB 3.1 Gen1 Overview (II) Equalization At both transmitter (TxEQ) and receiver (RxEQ) RxEQ training during initialization to accommodate range of channel conditions 03-17 Oscilloscope Training - USB, PCIe interface options

USB3.1 Gen1 Overview (III) Low power states with mechanism for exit to SuperSpeed Low Frequency Periodic Signaling (LFPS) LFPS is an asynchronous handshake Four packet types Link Management Packets (LMP) Transaction Packets (TP) Data Packets (DP) Isochronous Timestamp Packets (ITP) 03-17 Oscilloscope Training - USB, PCIe interface options Enhanced SuperSpeed USB uses four basic packet types each with one or more subtypes. The four packet types are: • Link Management Packets (LMP) only travel between a pair of links (e.g., a pair of directly connected ports) and is primarily used to manage that link. • Transaction Packets (TP) traverse all the links directly connecting the host to a device. They are used to control the flow of data packets, configure devices, and hubs, etc. Transaction Packets have no data payload. • Data Packets (DP) traverse all the links directly connecting the host to a device. Data Packets have two parts: a Data Packet Header (DPH) and a Data Packet Payload (DPP). • Isochronous Timestamp Packets (ITP) are multicast on all the active links. All packets consist of a 14-byte header, followed by a 2-byte Link Control Word at the end of the packet (16 bytes total). All headers have a Type field that is used by the receiving entity (e.g., host, hub, or device) to determine how to process the packet. All headers include a 2-byte CRC (CRC-16). All devices (including hubs) and the host consume the LMPs they receive. If the value of the Type field is Transaction Packet or Data Packet Header, the Route String and Device Address fields follow the Type field. The Route String field is used by hubs to route packets which appear on their upstream port to the appropriate downstream port. Packets flowing from a device to the host are always routed from a downstream port on a hub to its upstream port. The Device Address field is provided to the host so that it can identify the source of a packet.

USB - Layers 03-17 Oscilloscope Training - USB, PCIe interface options

Typical Debug Use-cases 03-17 Oscilloscope Training - USB, PCIe interface options

Typical Application Use-cases USB 3.1 Gen1 gets adopted now!! PC, consumer, mobile devices, automotive, industrial, etc. Developers have to trouble shoot missing links, incorrect signal content and need to debug SI Get some idea about signal waveforms Check protocol data down to bit level 03-17 Oscilloscope Training - USB, PCIe interface options

R&S®RTO-K61 USB 3.1 Trigger & Decode Option 03-17 Oscilloscope Training - USB, PCIe interface options

RTO-K61 - USB 3.1 Gen1 Trigger & Decode Option At a Glance Full support of USB 3.1 Gen1 at 5 Gbit/s Auto detection of the data rate and threshold Scramble / Descramble selectable Reliable triggering on protocol detail Selectable decoding layer: edges, bits, Scrambled or Descrambled Comma & Data Powerful search capabilities Most compact debug solution with RTO2064 and RT-ZM60 probe ME pricing: 1,990 € 03-17 Oscilloscope Training - USB, PCIe interface options

Decode Very easy setup Highlights: Auto CDR Display thresholds Various decode layers 03-17 Oscilloscope Training - USB, PCIe interface options

Trigger Comprehensive Search based SW Trigger Supports plenty of packet types 03-17 Oscilloscope Training - USB, PCIe interface options

Customer Use-cases and typical Product Configuration USB 3.1 Gen1 gets adopted now!! PC, consumer, mobile devices, automotive, industrial, etc. Developers have to trouble shoot missing links, incorrect signal content and need to debug SI Get some idea about signal waveforms Check protocol data down to bit level R&S product offering: RTO2064 RT-ZM60 + RT-ZMA10 solder-in tip module RTO-K61 USB 3.1 Gen1 T&D option RTO-K63 USB-PD T&D option 03-17 Oscilloscope Training - USB, PCIe interface options

Signal Integrity Debugging 03-17 Oscilloscope Training - USB, PCIe interface options

RTO Signal Integrity Debugging Capabilities Debugging tools: Realtime mask testing (standard capability) Serial pattern trigger (standard capability) HW CDR (optional) Jitter analysis (optional) 03-17 Oscilloscope Training - USB, PCIe interface options 1. An ideal reference clock without jitter is assumed for this specification. All Links are assumed active while generating this eye diagram. 2. Transition and non-transition bits must be distinguished in order to measure 15 compliance against the de-emphasized voltage level (VTXA_d). VTXA and VTXA_d are minimum differential peak-peak output voltages. 3. TTXA is the minimum eye width. The sample size for this measurement is 106 UI. This value can be reduced to 274 ps for simulation purpose at BER 10-12. 4. JTXA-MEDIAN-to-MAX-JITTER is the maximum median-to-max jitter outlier as defined in the 20 PCI Express Base Specification, Revision 2.0. The sample size for this measurement is 106 UI. This value can be increased to 63 ps for simulation purpose at BER 10-12. 5. The values in Table 4-7 are referenced to an ideal 100 Ω differential load at the end of the interconnect path at the edge-finger boundary on the add-in card (see 25 Figure 4-5). The eye diagram is defined and centered with respect to the jitter median. Exact conditions required for verifying compliance while generating this eye diagram are given in the PHY Electrical Test Considerations for PCI Express Architecture document.

USB Signalling with LF Sequence 03-17 Oscilloscope Training - USB, PCIe interface options

Standard SI Measurements on the USB Signal Stream Time and Voltage Measurement Cursor measurement, e.g. pulse width Automated measurement, e.g. rise time 03-17 Oscilloscope Training - USB, PCIe interface options

Eye Diagram and Histogram Measurements Fastest mask test according to USB spec. Utilize HW-CDR for triggering on continously extracted embedded clock Additional Histogram 03-17 Oscilloscope Training - USB, PCIe interface options

HW-CDR Option Application: Setup: Fastest Histogram and Eye diagram based on embedded clock triggering Can be combined with TIE measurement Setup: For USB 3.1 Gen1 use 2.5 Gbps nominal bit rate Select second order PLL 03-17 Oscilloscope Training - USB, PCIe interface options

Recommended Configuration 03-17 Oscilloscope Training - USB, PCIe interface options

Typical Product Configuration Oscilloscope: RTO2064 – 6 GHz oscilloscope Probes: RT-ZM60 – 6 GHz modular probe RT-ZMA10 solder-in tip module Application options: RTO-K12 Jitter analysis option RTO-K13 HW CDR option RTO-K61 USB 3.1 Gen1 T&D option RTO-K63 USB-PD T&D option 03-17 Oscilloscope Training - USB, PCIe interface options

Thank you.