Design of a polyvalent robust isolated input channel Jens Steckert for MPE-TM with contributions from J. Kopal, E. de Matteis, S. Georgakakis, F. Boisier & MPE-EP team

Topics Motivation / Overview Circuit design aspects Implementations Lab testing Real world measurements

Motivation Since last LHC upgrades, several project appeared QDS for FAIR magnet testing QDS for SM18 QDS for HiLumi Magnet quench detection Current lead protection SC link protection Projoint etc Traditional approach: one specific solution for each project New approach: “one size fits most”...

Requirements Sufficient resolution Sufficient speed for future projects (Nb3Sn etc.) Low latency Galvanic insulation up to 2.5kV/10min, 5kV/1s Input range +/-50mV ... > +/- 20V programmable gain No voltage divider to be able to detect broken taps Robust input protection ~1kV/1s differential

Speed vs. resolution 24 BS DC 22 new 600A 20 uQDS 18 BEWARE ! LOG scales 16 DQQDS nDQQDI DQHSU 14 ADC resolution [Bits] 12 10 8 6 4 2 10 100 1000 10k 100k 1M Sampling speed [Hz] Existing units had either high resolution OR high sample rate New channel design combines speed with resolution Oversampling yields additional bits 20bit@1M  24bit@3.9k* *only for noisy signals, all other errors won’t improve...

General uQDS architecture Versatile digital platform polyvalent insulated analogue input FPGA configurable QDS logic Interlocks polyvalent insulated analogue input . Communication interface polyvalent insulated analogue input Memory Flash 5..12 channels Polyvalent input channel is an integral part of the uQDS system

channel architecture and design details

General channel architecture powering DCDC analog chain ADC reference powering input protection digital isolators

Input topology Traditional input stages were based on single ended inputs and voltage dividers Fully differential inputs offer 2x the input range of single ended devices Higher input range allows for divider-less inputs Divider-less inputs enable pull-ups to detect broken taps/wires Classic input stage (BS, DS, DI etc) new input stage topology

Insulation and input protection Galvanic insulation ensured by Insulated DC-DC, 5kV peak Digital isolator, 4kV-6kV peak depending on model Inputs protected with depletion-mode MOSFET Limits input current to ~1-2uA  no big heating Input resistance <5k Ohm  reduces noise Survived quite some torture: ~1min @ 1.2kV, repetitive touching with HV

Choice of ADC technology SAR Sigma-delta Low power Simpler inner structure Available up to 20bit Some devices with excellent precision No latency Good experience in radiation environments Higher power (> x10 of SAR) Large filters and modulator Higher resolutions (24-bit quite standard) INL, gain & offsets often do not match resolution Inherent latency from filter chains Nightmare in radiation... Our choice: LTC2378-20 1Msp 20-bit SAR ADC

Implementation 1..4 Quite noisy gain stage Input buffer ADC driver Quite noisy ADC drive circuit not optimal, not made for high speed Common mode issues Non optimal reference and infrastructure circuits

Implementation 5.1 gain stage Input buffer ADC driver Gen 5 improved infrastructure a lot Good reference and DCDC found ADC drive based on FDA, quite good performance Still noise a bit too high Good overall stability

Implementation 5.6 Input buffer & gain stage ADC driver Fully differential design “Home made” fully differential PGA using FDA and precision resistor array Gain steps defined by resistor chain, implemented 1, 9, 45, 450 Excellent noise and linearity Less amplifiers used

some lab test results

Noise, implementation 5.6 5.6 G=1 inputs shorted Data sheet LTC2378-20 Bandwidth: 150kHz  5.6 noise comes close to data-sheet performance

Noise vs. Gain vs amplitude 5.6 Noise measured at 4 different gains and 3 amplitudes per gain Slight amplitude dependence observed  still to be investigated  At G=450 noise drops to ~2uV !

Bandwidth vs gain impl. 5.6 g=1 -3dB g=45 g=450 g=9 With higher gain, bandwidth drops  GBW of OpAmp For gain 450 bandwidth lower than expected

Linearity 5.6 G=1 linearity < 5ppm RTI (gain & offset calibrated) G=201 linearity < 35ppm RTI (gain & offset calibrated)  Excellent linearity (long term stability tests pending)

Dynamic performance Input: sine 2kHz 20Vpp THD: 0.0099%, SINAD 79dBc Input: sine 20kHz 20Vpp THD: 0.0067%, SINAD 80dBc Input: sine 50kHz 20Vpp THD: 0.0075%, SINAD 80.5dBc Input: sine 100kHz 1Vpp THD: 0.027%, SINAD 69.8dBc  Dynamic performance not so bad, more tests pending

Common mode rejection vs frequency isolated gnd + signal - generator common ground Common mode rejection ratio quite good Galvanic insulation yields 30-40db extra More measurements at different gains to be performed..

some real world tests

Real world tests: Flux jump measurement in Nb3Sn magnet zoom FWHM = 60us Flux jumps are violent but short  no problem with median filter

Real world tests: didt sensor prototype measurements Versatile platform + channel 5.1 in contious readout at G= 100 for didt, G= 1 for DCCT readout Digital 50Hz notch filter

Real world tests: didt sensor prototype measurements Versatile platform + channel 5.1 in continuous readout. G=1000 for didt sensor, G=1 for DCCT signal Digital 50Hz notch filter

Conclusions The step from 16 to 20bit with 5x bandwidth is quite a big one (every detail counts...) v5.6 shows quite good performance v5.1 & v5.6 real world tested showing good performance Specifications met v6.6 (shrink of 5.6) planned for this year A box with 12x v6.6 channels going to be next step