Introduction to Vivado Design Suite

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Presentation transcript:

Introduction to Vivado Design Suite

Vivado Design Suite Vivado is the new tool that only supports 7 series FPGA, UltraScale and all more recent families. Completely re-developed from scratch The algorithms for Vivado are implemented with having the ever-growing size of FPGAs in mind New deterministic Place and Route Algorithm All steps have the same view on a global data structure Vivado HLS: High-level sysnthesis tool Xilinx Design Constraints All tools in Vivado except SDK and Vivado HLS are integrated part of the GUI

ISE Vivado New integrated GUI All tools in Vivado except SDK and Vivado HLS are integrated part of the GUI

Vivado GUI

Creating a new project

Project manager

IP Integrator

Simulation: create testbench

Simulation: edit testbench

Running simulation

Specifying constraints: Specifying constraints XDC Consttraints (replacement of UCF) XDC constraints are a combination of: Industry standard Synopsys Design Constraints (SDC), and Xilinx proprietary physical constraints XDC constraints have the following properties: They are not simple strings, but are commands that follow the Tcl semantic. They can be interpreted like any other Tcl command by the Vivado Tcl interpreter. They are read in and parsed sequentially the same as other Tcl commands.

UCF to XDC Source: Vivado Design Suite Migration Methodology Guide (UG911) p 23

Creating or adding XDC file

Creating XDC file

Master XDC http://zedboard.org/support/documentation/1521

Design elaboration: I/O Planning

Design elaboration

Synthesis and the synthesized design

Implementation and the implemented design

Reports

Generating bitstream

Hardware manager: open target

Hardware manager: open target

Hardware manager: program device

Questions?