Updates on the R&D for the SVT Front End Readout chips F. Giorgi – INFN Bologna 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati Summary Strip readout architecture Investigated architecture Simulation results 3D pixel submissions SuperPix1 Apsel_VI 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
Strip Chip Architecture Updates on Job Status 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
Strip readout architecture under development BOLOGNA pixel-like hit extraction architecture Pre-trigger buffer array PISA Sparsifiers FE Ctrl logic Buf #k ... #1 4 bit ToT readout/slow control strip #127 strip #0 ~hit_rate * trig_latency BUF #1 Triggered hits only How many buffers? How many barrels? Asynchronous logic assumed: Triggered event size not known a-priori (thus readout time as well) 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati Simulation status All elements have been modeled on both sides VHDL for hit extraction system and slow control SystemVerilog for the strip FE logic and buffers Test Bench developed: Elements: Monte Carlo hit generator Slow control vectors for chip configuration and opearation Hit-IN / Hit-OUT lists for efficiency evaluation. Device Under Test Simulation Tool: ModelSim SE (allows mixed-code simulations) So Far Whole architecture integrated in simulation Simulated with L0 and L1 expected rates (safety factor included) 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
Test Bench Scheme 128 Strip channels MC generator Reduced and revisited version of the pixel Montecarlo generator FE logic Trigger buffers, TS tag/request handling ecc. MC generator 128 Strip channels FE logic and trigger buffer Hit-IN Readout ~ equivalent to: 4 pixel sub-matrices 256 rows 1 column (with minor revisions) Trigger handling Hit encoding Hit de-queue Hit-OUT Cross check 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
Only digital readout efficiency taken into account Simulations Tens of ms of operation simulated MC hit rate trimmed to 2 MHz/strip (L0) and 760 kHz/strip (L1) Trigger latency 6 us / trigger rate 200 kHz. Time stamp resolution: 30 ns Trigger buffer depth scan (8163264) Efficiency evaluation NB: No multiple hits allowed on the same strip for the same time interval. Only digital readout efficiency taken into account 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati Simulation results 2 MHz/strip : Layer 0 buffer size 16 32 64 buffered hits 3.8 M 12.9 M of which triggered 23363 76850 output triggered hits 14679 76849 triggered hit lost 8684 1 Efficiency (%) 62.8 99.9987 100 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati Simulation results 760 kHz/strip : Layer 1 buffer size 8 16 32 buffered hits 1.4 M 7 M of which triggered 8748 28829 output triggered hits 6788 28825 triggered hit lost 1960 4 Efficiency (%) 77.6 99.986 100 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
Vertical Integration -- 3D-IC submission 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
The 3D-IC sensors with digital sparsified readout 3D MAPS sensors (separate digital/analog tiers) allow a dense in-pixel logic Smarter sparsified readout can be implemented. The architecture we have developed can work both in data-push and triggered mode Designed to sustain 100 MHz/cm2 hit rate Time resolution down to 100 ns. 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati The 3D MAPS projects Apsel-VI MATRIX 96x128(2 sub-m. 48 x128) 5.2 x 10 mm (incl. scr. line) Rows divided in: 4 sparsifiers 32 rows for each sparsifier 8 zones for each sparsifier (Wzone= 4 pixels) SuperPix1 MATRIX 32x128 (2 sub-m. 16x128) 3.5 x 10 mm (inc. scr. Line) 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati Readout Few revisions w.r.t. INMAPS submission. The 2 sizes of readout have been tailored Both circuits synthesized by Synopsys Design Compiler Digital signal pads manually added to the compiled netlist Physical implementation (P&R) with Cadence Encounter tool. Post –layout netlist (including clock-trees, pads, buffers …) simulated with Modelsim. Some problems including the extracted parasitic. to be solved Anyway, static timing by Encounter converges well. 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati APSEL VI Floorplan matrix 5034 um x 9800 um die area 70 k Std-Cell readout Readout power estimate @ 50MHz – 200 MHz min 100 mW (1.08 V, +125C) slow max 200 mW (1.65, -40C) fast 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
APSELVI – Readout floorplan detail Horizontal Pitch = 146 um Vertical Pitch = 250 um Staggered rows VDD/VSS core rings 160 um thick 1.2 um spaced apart (twice as suggested by encounter tool) 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
APSELVI south-west side analog pads PAD List may change and can contain mistakes! Do not use as a reference APSELVI south-west side analog pads AVSS AVSS AVSS AVSS AVSS break break Inj1 outSH1 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
APSELVI south-east side analog padss PAD List may change and can contain mistakes! Do not use as a reference APSELVI south-east side analog padss AVDD AVDD AVDD AVDD AVDD break break Inj2 outSH2 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
APSELVI south side digital pads PAD List may change and can contain mistakes! Do not use as a reference APSELVI south side digital pads PVDD ChipAddr0 PVSS fastClk SCL RDclk Reset BCclk MLEna ChipAddr2 Trigger Reserved ChipAddr1 Read Left to Right PDVDD Data_out6 Data_out2 PDVSS Data_out5 Data_out1 Data_out15 Data_out10 PVSS Data_out0 Data_out14 Data_out9 Data_out4 DataValid Data_out13 Data_out8 Data_out3 GlobFastOR Data_out12 Data_out7 SDA Data_out11 PVDD 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
APSELVI – north side pads PAD List may change and can contain mistakes! Do not use as a reference APSELVI – north side pads break ANALOG PADS (Left to Right) DIGITAL PADS (Left to Right) PVSS PDVSS SR_DATA_IN SR_CLK SR_DATA_OUT PVDD PDVDD PAVSS IDAC PAVDD rif_ext_gm protP Inj3 Vfbk_pa protN outSH3 Inj4 sub outSH4 v_th vdrop1 vdrop2 rif_I_transc IbiasDAC 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati SuperPix1 Floorplan 3255 um x 9421 um die area 40k Std-Cell readout Readout power estimate @ 50MHz – 200 MHz min 70 mW (1.08 V, +125C) slow max 140 mW (1.65, -40C) fast 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
SuperpPix1 PAD Read Left to Right break break Reset PVDD BCclk MLEna PAD List may change and can contain mistakes! Do not use as a reference SuperpPix1 PAD Reset PVDD BCclk MLEna ChipAddr2 trigger Inj_clk ChipAddr1 PVSS ChipAddr0 fastClock SCL RDclk PAVSS PAVDD PAVSS PAVDD Read Left to Right break break PDVDD Data_out8 Data_out3 GlobFastOR PDVSS PVDD SDA Data_out13 PVSS Data_out12 Data_out7 Data_out2 Data_out11 Data_out6 Data_out1 Data_out10 Data_out5 Data_out0 Data_out9 Data_out4 DataValid
SuperPix1 – Matrix digital powering Followpin towards matrix power pads routed by Encounter tool 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati Conclusion Strip Strip FE architecture defined, modeled and simulated. Digital readout efficiency measured value (simulations): ~100% with buffer depth = 32 @ Layer 0 (2 MHz/strip) 3D Pixels: Readout circuits placed and routed Post layout circuit (clock-trees, pads) simulated (some problems with std-cell timing library) Static Timing analysis converging (Encounter) PADS disposition almost defined. Definitive routing when all custom blocks are closed. 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati Back-Up 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
Max peaking times (ns) at fixed strip efficiency M. Villa Target strip efficiency 97.6% 95% 91% SF=5 SF=1 L0 5 25 10 52 19 95 L1 15 74 31 156 57 286 L2 24 120 51 253 93 466 L3 66 329 121 605 L4 215 1077 455 Max 836 L5 361 1807 763 1403 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati
F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati MC gen self test MCgen CMP loopback Busy hit generated with a ToT = 14 another hit generated @ 19775 ns CMP not re-triggered total CMP length is 140 ns = prev. ToT (14) *10 ns ToT resolution busy_hit_count incremented by 1 rough inefficiency estimate due to occupancy by busy_hit_count/hit_count. 3/21/2012 F. Giorgi – 3rd SuperB Collaboration Meeting - Frascati