8085 interrupts

8085 Interrupts Maskable Non-Maskable Vectored INTR RST vectored TRAP RST5.5, RST6.5, RST7.5, TRAP

Interrupt process enable by writing EI. mp checks INTR line at each instruction. if INTR is high, mp completes the current instr, disables Interrupt Flip-flop, sends INTA signal. An RST instru is inserted by INTA through external hardware. Mp saves the memory address of the next instru into stack. Program control is transferred to CALL location. The service routine starts at CALL location. At the end of the subroutine Int Flag is enabled again by EI instru. The last instr of the subroutine is RET to trasfer back the prog control to its orginal address.

RST instructions 8 RST instructions +5v EF to data bus 1 1 1 1 1 1 1 Mnemonics Binary code Hex Call Location D7 D6 D5 D4 D3 D2 D1 D0 RST0 1 C7 0000 RST1 CF 0008 RST2 0010 RST3 DF 0018 RST4 E7 0020 RST5 EF 0028 RST6 F7 0030 RST7 FF 0038 +5v 1 1 EF to data bus 1 1 1 1 1 Enable

Write a program to count continuously in binary with one second delay between each Count. Service routine at XX70H to flush FFH five times when the interrrupt occurs with some appropriate delay between flash Main program Service routine LXI SP, XX99H EI MVI A, 00H NXTCNT: OUT PORT1 MVI C, 01H CALL DELAY INR A JMP NXTCNT XX70: SERV: PUSH B PUSH PSW MVI B, 0AH MVI A, 00H FLASH: OUT PORT1 MVI C, 01H CALL DELAY CMA DCR B JNZ FLASH POP PSW POP B EI RET Interrupt instr: EF At 0028H JMP xx70H

Issues in implementing interrupts Is there a minimum pulse width required for the INTR signals? MP checks INTR, one clk period before the last-T state of an instruction cycle, therefore, the INTR pulse should be high at least for 17.5 T-states. How long can the INTR pulse stay high? Can the MP be interrupted again before the completion of the first interrupt service routine?