DIF – LDA Command Interface Julie Prast, Guillaume Vouters, Rémi Cornat, Bart Hommels, Mathias Reinecke, Frantisek Krivan, Marc Kelly, Matt Warren 12.12.2008

Introduction (DIF interfaces) Hardware defined by DIF task force Defined by ASIC designers How data is sent is defined by DAQ designers, but what is sent (for DIF/detector operation) was undefined. Command definition was necessary, common for DHCAL, ECAL and AHCAL. Also needed for DOOCS development very soon. 12.12.2008

Command Interface - Structure Prototyping Debugging Final Setup - DIF clock (from LDA): 100MHz (40-120MHz). - Standard data transfer: 8b/10b channel-coding. Trigger/RAMFull: uncoded. USB interface emulates LDA interface (clock-source: free of choice). 12.12.2008

Data / Command Transfer I Two types of data transfer “frames” are defined between LDA and DIF: 1. Fast Command Frame (16-bit length): Used for link synchronization, timing-critical commands and broadcasts to the DIFs only. Several Ks and „special sequences“ are predefined. See http://www.hep.manchester.ac.uk/u/mpkelly/calice/lda/Calice_LDA_Overview.html 12.12.2008

FAST Commands for the DIF not all shown … Command list has 5 sections: General commands, ECAL specific commands, DHCAL specific commands, AHCAL specific commands, DCC identifiers. 12.12.2008

Data / Command Transfer II 2. Block transfers (length not fixed): Used for standard commands and data transfer (e.g. slow-control, result data) between LDA and DIF packettype: defines block to be: block data / generic command / command ECAL only / command DHCAL only / command AHCAL only / Command (Block) is for DIF-DIF Link / data is DIF firmware / … pktID: numeration of sent blocks, used to identify block losses. type_modifier: command definition. This is the address of the respective command register. data_length: Number of 16-bit vectors sent in the “data”-section of the block. data: 16-bit data vectors, e.g. slow-control data for the ASICs CRC: cyclic redundancy check (look for transmission errors). 12.12.2008

BLOCK Transfer Commands not all shown … Sections: General, ECAL specific, DHCAL specific, AHCAL specific 12.12.2008

Command Registers in DIF For each command (LDA to DIF) the DIF has a dedicated command register. The address of this command register is defined - by the X in the incoming DX.Y command word for FAST Commands - by the type_modifier for BLOCK Transfer Commands. Command registers are 16-bit, and can be subdivided for several functional purposes. 12.12.2008

Command Register Example power_on, BLOCK Transfer command, address 0x0002 12.12.2008

Slow Control / Readout Two sets of slow-control data can be stored at the DIF for each partition (slab) in external Flash memory. Time-optimized (re-)programming of slabs (very simple) RAM in DIF FPGA is too small to store a full set of result data (slab readout) Readout of slabs and data transfer to LDA in parallel. From the DIF task force 12.12.2008

Pre-Spill Indication I DIF needs time to prepare for data-taking (power-on, check configuration, maybe „reset Bunch Counter“, change to ACTIVE mode). „pre_spill indication“ is sent before the actual „start_acquire“ from the DAQ (via LDA): t.b.d. From the DIF task force 12.12.2008

Pre-Spill Indication II If „pre_spill indication“ is not used, „start_acquire“ is sent exactly XXX clock cycles in advance to the bunch trains. => Choose operation mode via DIF Control Register t.b.d. From the DIF task force 12.12.2008

Conclusions Document available (current version 1.7) defining the command interface LDA-DIF, as well as basic DIF operations. DAQ people greatly supported the development! („Many thanks!!“). See: http://adweb.desy.de/~reinecke/DIF_Firmware_vers1_7.pdf Slab- (partition-) interface is already defined by ASIC designers DIF hardware specifications have been agreed on in the DIF task force. - Naming conventions within DIF firmware code under development. DIF firmware development can take place now in excellent conformity between the detectors DHCAL, ECAL and AHCAL! 12.12.2008