Tips for Optimizing your MPiec Application Program

Slides:



Advertisements
Similar presentations
1/1/ / faculty of Electrical Engineering eindhoven university of technology Architectures of Digital Information Systems Part 1: Interrupts and DMA dr.ir.
Advertisements

1 Lab Session-IV CSIT-120 Spring 2001 Lab 3 Revision and Exercises Rev: Precedence Rules Lab Exercise 4-A Machine Language Programming The “Micro” Machine.
Software Development and Software Loading in Embedded Systems.
Chapter 91 Memory Management Chapter 9   Review of process from source to executable (linking, loading, addressing)   General discussion of memory.
File System. NET+OS 6 File System Architecture Design Goals File System Layer Design Storage Services Layer Design RAM Services Layer Design Flash Services.
Atmega32 Architectural Overview
Lab 1 – Assembly Language and Interfacing Start date: Week 3 Due date: Week 4 1.
1 I-Logix Professional Services Specialist Rhapsody IDF (Interrupt Driven Framework) CPU External Code RTOS OXF Framework Rhapsody Generated.
DELTA TAU Data Systems, Inc. 1 UMAC TurboTurbo PMAC PCIGeo Drive Single Source Machine Control motion logic data Power PMAC Project Management November.
RM2D Let’s write our FIRST basic SPIN program!. The Labs that follow in this Module are designed to teach the following; Turn an LED on – assigning I/O.
1 Computing Software. Programming Style Programs that are not documented internally, while they may do what is requested, can be difficult to understand.
Computer Systems Organization CS 1428 Foundations of Computer Science.
IT253: Computer Organization Lecture 3: Memory and Bit Operations Tonga Institute of Higher Education.
Cosc 2150: Computer Organization Chapter 6, Part 2 Virtual Memory.
Chapter 8 – Main Memory (Pgs ). Overview  Everything to do with memory is complicated by the fact that more than 1 program can be in memory.
© Janice Regan, CMPT 300, May CMPT 300 Introduction to Operating Systems Memory: Relocation.
Understanding and Applying Camming Techniques with the MP2000iec and MotionWorks IEC 1 Yaskawa Electric America Understanding & Applying Camming Techniques.
Silberschatz, Galvin and Gagne ©2009 Operating System Concepts – 8 th Edition, Chapter 3: Process-Concept.
File Systems cs550 Operating Systems David Monismith.
Operating Systems (CS 340 D) Dr. Abeer Mahmoud Princess Nora University Faculty of Computer & Information Systems Computer science Department.
Driving Value SMC-3010 to MP2600iec Conversion PN.MP2600iec.01.
OPERATORS IN C CHAPTER 3. Expressions can be built up from literals, variables and operators. The operators define how the variables and literals in the.
File I/O. I/O Flags Flags are passed to give some information about how the file is to be used. – Read only file – flag=0x0 – Write only file – flag=0x1.
Chapter 1: Introduction to Computers and Programming
SPiiPlus Training Class
Introduction to Kernel
Yaskawa Electric America Understanding & Applying Camming Techniques
SLC/VER1.0/OS CONCEPTS/OCT'99
Architectures of Digital Information Systems Part 1: Interrupts and DMA dr.ir. A.C. Verschueren Eindhoven University of Technology Section of Digital.
Multiprocessor System Distributed System
Processes and threads.
OCS Configuration Software:
Atmega32 Architectural Overview
Chapter 8: Main Memory.
Chapter 3: Process Concept
Welcome to Yaskawa Electric America’s Training Café Express
Overview of Computers and Programming Chapter 1
Operating Systems (CS 340 D)
Process Management Presented By Aditya Gupta Assistant Professor
Other Kinds of Arrays Chapter 11
Introduction to Computers
CSCI 161: Introduction to Programming
Operating Systems (CS 340 D)
User-Defined Functions
Module 9: Virtual Memory
Interfacing Memory Interfacing.
Operation System Program 4
Lecture 2: Processes Part 1
Processor Management Damian Gordon.
Memory Allocation CS 217.
Operating System Concepts
Process & its States Lecture 5.
Operating Systems.
Yaskawa Electric America
ECE 3430 – Intro to Microcomputer Systems
Creating Computer Programs
Chapter 3: Processes.
8051 ASSEMBLY LANGUAGE PROGRAMMING
Little Man Computer There’s a little man in the mailroom that follows each instruction to the letter but he can only follow one instruction at a time.
Software Development Environment, File Storage & Compiling
Chapter 3: Processes Process Concept Process Scheduling
Creating Computer Programs
Processor Management Damian Gordon.
Structure of Processes
UNIT 1 First programs.
Lecture 20: Representing Data Elements
In Today’s Class.. General Kernel Responsibilities Kernel Organization
Module 12: I/O Systems I/O hardwared Application I/O Interface
Introduction to Multi-Tasking
Chapter 1: Introduction to Computers and Programming
Presentation transcript:

Tips for Optimizing your MPiec Application Program Part 1: Memory Allocation & Optimization Task Timing Analysis Function Block Error Interlocking Hosted by: Kevin Hull Nishant Unnikrishnan Name: Company: Address: Phone:

Agenda Maximizing Program Performance & Robustness Tips for Understanding and Managing Controller Memory Total System Memory Global Variables Compiled POU Code POU sizes Cam Memory Maximizing Program Performance & Robustness HIRES_TASK_TIMING_INFO_ARRAY Increase Troubleshooting Effectiveness with ErrorID

(Memory available to user) Memory Allocation Out of the box MP2300Siec (Memory available to user) 11,333,888 2,964,480 The actual memory available to the IEC application is cut by half. This allows the controller to do “Download Changes” and swap the project and data on the fly.

Camming Good Questions…. Q1) Is there a limit to how many points we can put in one of our Cam tables? Q2) What is the memory size where we would store the cam tables? Q3) Are Cam tables stored in RAM or Flash or either (maybe RAM if marked retained)?

Camming

Camming Cam Memory Q & A Q1: What is the data type of the .csv, I think LReal.  If so, that is a lot more bytes per point  ( A long real, is that 8 bytes per point ? ) A1: The data in the CSV is ASCII, not binary.  This means that a master / slave pair like 12.456678,67.21344323 occupies 21 bytes (the character count plus a carriage return for a total of 22 bytes.  A CSV file may or may not be larger than binary depending on how many actual characters of precision are required.  On the FLASH side, (what you see in the project archive) is a CSV.  CSVs are loaded into the motion engine (using Y_CamFileSelect) and converted to binary in the SDRAM.

Camming Cam Memory Q & A Q2: Are the master points pre-defined in equal increments?  A2:The master / slave data does not need to be equal increments This can save memory if the required motion has a period with a simple relationship. (Straight Line) Q3: For a 1,000 point cam, will there be 2,000 total points (1,000 master and 1,000 slave) ? A3: Every slave requires a master and slave data value. Together, each Master / Slave value is a “cam point.”

(24) CSV cam files in flash Large Program Specs (68) CamSegmentStruct 12,868 bytes each 875,024 bytes total 21 “Large” POUs Nearly 64 Kbytes of compiled code each 1,260,000 bytes (24) CSV cam files in flash ASCII master slave values 2,137 data points in each 77,436 bytes in each file 1,858,464 bytes in flash (4) Cyclic Tasks (16) Servo Axes 4 mSec Mechatrolink

Camming Cam Memory Q & A Q4: With Y_CamIn, how many points can I generate? A4: This is not a simple answer, the answer depends on several factors, such as number of cam tables, size of application program, and more. But…   I would imagine you could make a cam file with 32768 points.  As a CSV, lets estimate the size to be 22 bytes * 32768.  This would be about 721K.  Its possible three or four cams this size can be loaded in the FLASH at once.  That would be almost 3 MB. When one of these cams is copied to the SDRAM for use by the Motion Engine using Y_CamFileSelect, it would occupy (8 + 8) * 32768, or 524,288 bytes.  You really only need one or maybe two per axis in the Motion Engine (SDRAM) at once.  You can always delete them (using Y_ReleaseCamTable) and reload when necessary.

Error: Exceeded the Data Area SDRAM Allocation: Possible Issues Error: Exceeded the Data Area What does it mean? The memory required for the IEC application is too large for the space allocated in SDRAM.

SDRAM Allocation: Possible Issues

IEC variable memory allocation SDRAM Allocation: Possible Issues IEC variable memory allocation If the memory allocation is set to 3.2 MB, you will get this message when starting a new project or opening an existing project which is configured for 1.6 MB allocation If the memory allocation is set to 3.2 MB, you will get this message when starting a new project or opening an existing project which is configured for 1.6 MB allocation These Errors basically mean that memory configuration settings between MotionWorks IEC and your project are out of sync

IEC variable memory allocation SDRAM Allocation: Possible Issues IEC variable memory allocation You may have too many large variables (Data Types) defined but never used. Remove unused variables Recycle large variables where possible Variables of type Y_MS_CAM_STRUCT can be recycled!

Task Timing in MPiec Controllers IEC Application task priority: 0 - 16 Set Watchdog Time = Interval Detailed help on task priorities in section 1.12 of Hardware Configuration help

Task Timing in MPiec Controllers Slow task Medium task Outputs written* Inputs read* Fast task (FT) MLINK task MECHATROLINK Startup FT Start FT end Fast Priority 0 Medium Priority 7 Medium task start Medium task end Slow Priority 15 Slow task start Slow task end Default task start Default * If IO is assigned to medium task

Task Timing Monitoring Variables ProconOS Controllers: MP2300Siec and MP2310iec Structures for real time task timing information available in the global variable table in MotionWorksIEC 2.5 Variable name DATA TYPE ADDRESS Task timing in ms Task Timing in us MECHATROLINK II Timing in us

Task Timing Monitoring Variables ECLR Controllers: MP2600iec and MP3xxxiec Structures for real time task timing information available in the global variable table in MotionWorksIEC 2.5 Variable name DATA TYPE ADDRESS Task timing in us DPRAM / MECHATROLINK III Timing in us

Add to Watch Window/Logic Analyzer Task Timing Monitoring Variables Add to Watch Window/Logic Analyzer Select the relevant structures

Explanation of Task Timing Variables Task Timing at Standstill Task Timing with Motion Motion

Explanation of Task Timing Variables 2729 us 726 us 1140 us 4330 us Motion Command Timing info before motion commanded Medium task interrupted Medium task interrupted Slow task interrupted

Explanation of Task Timing Variables Y_CamIn.Execute CamShift

Applying PLCopen rules to your application code Interlocking Logic for Execute type function blocks ErrorID should permeate up to the User Interface

Interlocking Logic for Exe Type Blocks In our hurry to get programming done faster so that motion can be tested sooner, we ignore rules governing PLCopen blocks User Input from HMI ShearMVError Exe 6 ms

Model for logic that can convey function block status effectively Interlocking Logic for Exe Type Blocks Model for logic that can convey function block status effectively Permissive bit * Initiator bit Latch when FB is functioning properly Latches when FB is in error or is aborted The ‘Permissive’ bit can be a status that allows the FB to run. It could be a user controlled bit for user acknowledgement of FB status. It stands for all conditions that must be met for the block to run

Interlocking Logic for Exe Type Blocks Live Demo

Function Block Status Flow Execute Done/Busy/Error/ErrorID Application Code User Library function block Firmware Library function block

Function Block Status Flow 1) Keeping the Error ID latched on VAR_OUTPUT 2) Passing the ErrorID upstream to the application code

Refer to the Yaskawa Toolbox for templates Function Block Status Flow Refer to the Yaskawa Toolbox for templates www.yaskawa.com/iectb

Function Block Status Flow Application Code User Library function block

Thank You! Name: Company: Address: Phone: PP.MPIEC.01 | Rev 1.00 | Date: 03/31/2011 | ©2010 Yaskawa America, Inc. All rights reserved.