Design and Analysis of Low-Power novel implementation of encryption standard algorithm by hybrid method using SHA3 and parallel AES

Objective The aim of the research is to design and analyze an encryption standard algorithm by hybrid method using SHA3 and parallel AES The aim will be also on high speed data and usage of high end Field Programmable Gate Array (FPGA) based advanced encryption standard (AES) design.

Abstract The proposed design will introduce a Parallel processing of the key expansion technique. To eliminate the coding complexity present in the existing method a novel implementation of AES (Advance encryption standard) algorithm will be proposed. Enhanced throughput is achieved by proposing a hybrid method using SHA3 and parallel AES.

Introduction In today’s world, electronic communication has become a necessity in both work and Personal lives, especially since the advent of the Internet. Cryptography deals with securing electronic communication. A major part of cryptography is hash functions. The design of these functions causes a drastic change in the output when an input is even slightly changed. Applications of hash functions include file integrity, password verification, file identification, pseudorandom number generation, as well as key derivation.

Scope of implementation Due to the algorithms used in their computation, hash functions have poor speed performance on general purpose processors, such as central processing units (CPUs) in computers Can be implemented in dedicated hardware such as application specific integrated circuits (ASICs), or they can be designed with reconfigurable hardware, with field programmable gate arrays (FPGAs)

Existing Method: A lot of earlier work related to FPGA implementations of the SHA-3 has been reported since 2012. Most of these implementations are optimized for high throughput and few are known about compact designs. In terms of area, the design has the lowest hardware resources utilization that occupies 188 slices and operates at 285 MHz frequency. KrisGaj et al. design implemented in Virtex-5 operates at the maximum frequency of 238.4 and requires 24 clock cycles. The throughput of this design is 1.0805 Gbps because of its large area utilization of 1229 slices; therefore its TPS is 0.879 which is very low. The compact implementation of SHA-3Keccak) was published in which reported results of SHA-3 or Virtex-6 and Spartan-6 FPGAs. They show the implementation results for both 256-bit and 512-bit digests.

Existing Method: Wenly consider the implementation of SHA-3 on Virtex-6 for512-bit digest which offers the frequency of 285 MHz and throughput of 0.08 Gbps which is considerably much less than the results presented in paper. The implementation reported in G. Provelengios et al. for Virtex-5 operates at the maximum frequency of 285 MHz with high area consumption 2573 slices. This design needs 25 clock cycles and has the high throughput of 5.70 Gbps but the TPS of this design is 2.21 that is very low due to high area consumption

Existing Method: K. Latif et al. gives the implementation results of Keccak-512 design when implemented in Virtex-5, and outline the better throughput of 6.32 Gbps because of the reduced clock cycles. This design utilized 1197 slices and TPS of the design is 5.27 Hom. et al gives the throughput of 6.56 Gbps on Virtex-5 and its TPS is 5.37. The previous reported designs does not provide resource Efficient solution in term of hardware as these designs utilized a lot of slices that can be reduced efficiently. These designs have very low TPS and need improvement.

Existing Method:SHA1 In 2003, Sklavos et al. worked to implement the SHA-1 function on an FPGA. The model was designed using VHDL and synthesized on a Xilinx 2V500FG456 FPGA. The design implemented a pipelined structure of the algorithm. The result was a throughput of 1339 Mbps, which was a 140% speedup compared to previous FPGA results, and about 1125% speedup compared to the CPU result. Li et al. published a DFA attack against the symmetric block cipher SHACAL. This block cipher substantially consists of the compression function of the hash function SHA1 except for the final addition operation. When using the SHA1 compression function as a primitive in a keyed hash function like HMAC-SHA1 [17] or in a key derivation function it might be of some interest if the attack of Li et al. also applies to the SHA1 compression function

Existing Method:SHA In 2010, Paris Kitsos; Nicolas Sklavos worked to implement SHA-3 candidates, which is one of the most critical issues, regarding the adoption of the SHA-3 standard. Comparisons, in terms of hardware terms are given in detail, through this work. Feng Ge et al. published a design and implementation of low-power and high-speed security hardware cores for the Advanced Encryption Standard (AES) and the Secure Hash Algorithm (SHA1). Three Register Transfer Level (RTL) circuit techniques, namely, Application Specific Register Reduction (ASRR), Locally Explicit Clock Enabling (LECE), and Bus Specific Clock (BSC) are proposed

Existing Method:SHA In 2005, Kakarountas et al. improved the performance of the SHA-1 function even further. The model was implemented on a Xilinx V150BG352 FPGA using an HDL design methodology. The results obtained was a throughput of 2526 Mbps, a roughly 37% increase over comparable designs. The area needed was only slightly more than other designs as well. Harris E. Michail et al. published a a Totally Self-Checking (TSC) design is introduced for the SHA-256 hash function, suitable for harsh environments The achieved fault coverage is 100% in the case of odd erroneous bits. The same coverage is achieved for even number of erroneous bits, if they are appropriately propagated. Performance measurements are reported for ASIC and reconfigurable technologies

Existing Method:SHA In 2006, Yiakoumis et al. produced a VHDL model of a key- hashed message authenticate code (HMAC), which is a direct application of the SHA-1 algorithm. The design was synthesized on a Xilinx Virtix-II FPGA. The goal was to design a HMAC with a high throughput but a small size. This result is about 17% faster than comparable HMAC designs. It was also the first SHA-1 implementation to reach 1 Gbps throughput without the use of pipelining. . In 2009 Lee et al. worked to implement an SHA-1 module with a two-unfolded architecture. In this technique there are two hashing cores that work in parallel. One handles the pre-computation, while the other handles the current hash cycle. There is no dependency between the two cores in a single step. The result speed that was achieved was 6040 Mbps on a Xilinx Virtex-II XC2V1000 FPGA Comparable designs using similar techniques were 26% slower in their hash computation. The area was also decreased from similar designs as well. The proposed model was 32% smaller than previous work

SHA 3 The third family of SHAs standardized by NIST is SHA-3. It was finalized into a published standard in August 2015. The goal of this family is not to replace SHA-2, but supplement it with alternative algorithms. When choosing the algorithm to use in the standard, NIST held a contest for various functions. The winner of that contest was the Keccak family of sponge functions which has now been used to implement the SHA-3 algorithm. The Keccak sponge function has a much different structure compared to the Merkle–Damgård construction of SHA-1 and SHA-2.

AES In 2001 NIST recommended aRijndael algorithm as an Advanced Encryption Standard (AES) to replace the Data Encryption Standard (DES) . The Advanced Encryption Standard (AES)algorithm has a set of computational steps which the data undergoes during encryption and Decryption process. The software implementation of Advanced Encryption Standard (AES) algorithm would be a very slow process and consume a large amount of processing time. Thus, the Advanced Encryption Standard (AES) algorithm can be implemented on two hardware approaches: Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGA).

FPGA Implementation issues on AES FPGAs inhibit inherent parallelism and are more effective in terms of cost than ASIC design as they are re-configurable. Several software and hardware implementations of Advanced Encryption Standard (AES) have been reported. But hardware implementation is more secured, provides flexibility and ease of Implementation. The implementations of Advanced Encryption Standard with less area and high throughput on a parallel, pipeline and sequential architecture is advantages.

Block diagram of AES Encryption and Decryption

Proposed Method: In this work we will propose a novel implementation of AES (Advance encryption standard) algorithm with reduced coding complexity and enhanced throughput by hybrid method using SHA3 and parallel AES. Parallel processing of the key expansion technique will increase the speed and throughput will be high. Algorithm will be implemented on Xilinx virtex kit. For additional support on encryption and decryption MATLAB simulations will be utilized.

Software & hardware To be USED Quartus tool Matlab Virtex KIT

Conclusion Low power dissipation with comparable speed performance will be achieved. Area,delay-overhead and power dissipation are majorly concerned. A detailed survey on existing methods were done . A hybrid method is formulated based on AES and SHA3.

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