Overview and Status ATLAS Pixel Detector Chiara Meroni INFN-Milano ATLAS Pixel Collaboration

The ATLAS Pixel Detector ~1850 mm ~380 mm The Pixel Detector is the vertex detector for the ATLAS experiment. It consists of three barrel layers (B-layer at R=5.1 cm from the interaction region) and six disks, covering with three precise measurement points the region up to 2.5. There will be 1456 barrel modules and 288 forward modules, for a total of 80 million channels and a sensitive area of 1.7 m2. Modules will operate in an environment temperature below 0ºC and within a 2T solenoidal magnetic field. Barrel modules are tilted by 20º in the R plane to overcompensate the Lorentz angle.

TDR Requirements Radiation hardness: NIEL > 1015 1 MeV neq/cm2 500 kGy Technical Design Report specification were: Rf resolution 13 mm, efficiency better than 97% at end of lifetime, analog information was a high priority option. Given the 25 ns beam crossing rate at the LHC: must be able to assign each hit to the proper bunch crossing; must be able to store the hit information during the trigger latency time of ~100 beam crossings. Equivalent to 10y operation for the external pixel layers (R=8.9 and 12.1 cm) B-layer at R=5.1 cm will be a factor three more irradiated.

Module concept Module Controller Chip Flex hybrid Sensor 16 FE chips A module is the elementary self consistent detector unit. It consists of a silicon sensor read-out by 16 front-end (FE) chips connected via bump bonding (either SnPb at IZM, Berlin, or In at Selex, Rome). Data digitization is performed locally by the FE.Information from and to the FEs passes through a Module Controller Chip, which also performs the event building. All communications use low voltage differential signal on micro-cables before being converted in optical signals at the end of the whole pixel detector active area, Opto Board. Module Controller Chip Flex hybrid Sensor 16 FE chips Pigtail HV connection

Rad-hard Sensors Sensor modules consists of 47232 n+ pixels ( 50 m  400 m) on n-substrate, having an active area of 60.8 × 16.2 mm2. Pixels are insulated by a moderated p-spray implant. For sensor testing all pixel can be kept equipotential by a bias grid. In order not to loose coverage, special pixel layout (long and ganged pixels) has been chosen for the interchip regions (>200m). Production of 2500 sensors as been finished at CiS, Germany, and ON Semiconductor (TESLA), Czech Republic. long ganged

Rad-hard FE Electronics The front-electronics chip, FE-I, is built in 0.25 m IBM technology: Each chip reads out 2880 pixels, arranged in column pairs. Each pixel cell consists of a fast preamplifier followed by a discriminator It performs a sparse readout and store hits in EndOfColumn buffers, until the level 1 trigger latency is expired. Threshold can be adjusted by a 7-bit tuning DAC in each channel. 8-bit pulse height information is obtained by the Time-over-Threshold technique. ToT uniformity is obtained by a 3-bit tuning DAC On wafer testing measured yield is 81% Dicing, thinning, dicing introduced a further 85% reduction 48 wafer production provided all the necessary FE( >45000 chip) For a module noise is tipically : 150 e for standard pixels 170 e for long pixels 270 e for ganged pixels After irradiation, it is ~ 250 e, increase is due to the additional leakage current.

Bump bonding AMS - In IZM – PbSn FE electronics is connected to the sensor cells using bump bonds. Two techniques, from different manufacturers have been used for production modules: In bumps by Selex (ex Alenia-Marconi Systems), Rome PbSn bumps by Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration, Berlin Bumping defects can be investigated by X-ray inspections, or electrical tests, and now are very rare: the production contract fixes a rejection ratio of 150 faulty bumps/modules (0.3%). For both bump-bonding technologies, the pixel collaboration and the manufacturers have developed reworking techniques to replace damaged or not conforming FE chips. Global yield after reworking is 94% AMS - In IZM – PbSn

Module Controller Chip and FLEX Hybrid The Module Controller Chip is built in the same technology as the FE. Validated SEU resistance : all critical registers are tripled and use a majority decision logic; in the FIFO’s, where data are stored, a bit-flip safe encoding is used to unambiguously disentangle hits (for which a small corruption rate is acceptable) from event separators (whose loss would cause DAQ misalignment) At the PS irradiation facilities MCC were run for the equivalent of 100000 s at the B-layer, without the need to reconfigure the chip. No. of transistors: 880 k Dimensions: 6840 x 5140 mm2 MCC-I2 The MCC and decoupling capacitors, temperature sensors and resistors needed by the LVDS buffers, are mounted on flex hybrids (Dyconex, CH) which are glued on the backside of the sensors Shown is the support card used for module charactherization.

Test Beam Results Production modules have been tested after irradiation to: NIEL = 1015 1 MeV neq/cm2, dose = 500 kGy Device properties tested in a 180GeV/c hadron beam: efficiency (TDR requirement >97%): >99.9% before irradiation 97.8% after irradiation (@500V, already fully depleted) charge collection after irradiation: 87±14% at 600V , if a controlled annealing is performed during the LHC shutdown resolution (TDR requirement < 13 m): 7.5 m at 10° incidence before irradiation, 9.7 m at 15° incidence after irradiation, requires hit duplication (10% increase in occupancy) Efficiency of irradiated detectors has also been measured in an LHC-like particle flux: the readout architecture is verified efficiency is not affected by occupancy even at B-layer rate different sources of losses start to show up above 0.21 hits/cp/bx (+23% with respect to the B-layer occupancy) onset of inefficiencies is gradual and it does not exceed 3% even at an occupancy 65% higher than B-layer.

Module Production Module production is almost finished: need is 1744 modules Production yield is ~ 93% High quality has been obtained Modules are ranked to install the best on the B-layer and disk1, ranking =60  0.1% of dead pixel

PIXEL DETECTOR PACKAGE The active elements are assembled in a complex mechanical structure : The Pixel Detector Package Beam Pipe Pixel Frame Barrel Half Shells Disk Sectors Service Panels Beam Pipe Support Structure (BPSS) Inserted in the Pixel Support Tube Evaporative cooling (C3F8) All structures are carbon composite with Al cooling tubes integrated in the local supports Disk Rings Endplate Endcone Disk Frame Barrel Frame Disk Ring Mounts Sectors Barrel Shells Staves “PIXEL DETECTOR”

Pixel End Cap All 6 disks have been assembled in LBL Sector assembly (1/8 of a disk): 6 modules are mounted on carbon-carbon plates, sandwiching the cooling pipe. All 6 disks have been assembled in LBL ENDCAP C is now at CERN Include 144 modules Will be used for a first commissioning of the Pixel Detector

Pixel Barrel L2 Layer L1 Layer B Layer The barrel frame, made of carbon fiber laminate with ultra high modulus (CFRP), will hold the staves L2 Layer L1 Layer B Layer Stave = 13 modules aligned on a shingled carbon-carbon support All the staves are identical up to the cabling phase The basic unit for the integration is the bi-stave, i.e. 2 staves linked by a unique cooling tube

services support are also shown Barrel Integration April 2005 – 2 prototype bistaves on 1 halfshell services support are also shown

Barrel Integration April 2006 2 bistaves mounted on L1 half-shell

Details

After 30% of stave production, significant leaks found in the end regions of some staves initiated a deep investigation. Leaks and corrosion were found even in the middle of some stave. The origin was in the brazing of the cooling fitting followed by not accurate enough QC procedure Strategy to recover was following a triple path: Insertion of a new pipe in the already loaded stave to restore integrity, after cleaning and passivating the existing corroding pipe. Repair: replace the present cooling pipe with a new pipe, via a controlled delamination of carbon-carbon structure and a subsequent re-assembly. New Staves: to compensate for the losses All need new cooling tubes and fitting After a very dedicated effort , the stave production resumed Full support from ATLAS that modified the schedule to delay the Pixel insertion to the very last moment (03/07)

112 staves are necessaries, up to now : 27 staves have been inserted Inserted stave detail 112 staves are necessaries, up to now : 27 staves have been inserted 39 staves (new+repair) have been loaded Loading and testing time greatly improved ~1 week

Pixel services A lot of design effort is going also in the readout , power and control system The power supply system has been designed to balance between high granularity and cost . In the implemented solution a single power supply channel may power up to 7 modules (sector or halfstave) . The data stream are optically transferred. One optoboard/halfstave at the detector side convert the electrical signal. A custom supply (SC-Olink) for 2 low current channel has been developped For the HV a commercial solution (Iseg, EHQ F107n-F, 16ch/mod) has been adopted

Low Voltage Regulation Station For Low Voltages a solution with a poorly regulated power supply in the counting room, (Wiener, Mara OM11.005) serving a remotely programmable ‘ regulation station’ providing individual floating outputs, with low ripple, has been designed. Regulated output are needed to protect the deep submicron FE from transients. The main boards house 16 ST voltage regulator (LHC4913 +) and provide ~1A@2V, with 10mV step A controller board, based on ACTEL APA075 FPGA comunicate via CANBUS interface with the DCS The system is rad-tolerant upto (NIEL > 1012 1 MeV neq/cm2)

Services integration PP1 region and service panels – Complex interface of the thermal controlled region with feedtrough of power cables,(>5K ), opto fibers (>3K), 80 cooling loops R=45cm A prototype is being assembled and checked at CERN , to be used with the Pixel End Cap on surface

A 3 hit Pixel Detector is on its way to record LHC events in ATLAS Conclusions Measured Pixel Modules properties fulfill requirements Production steps are now completed or under control End Caps are nearly complete Integration on halfshells has started, based on the preliminary experience is feasible to improve the foreseen rate Services design is complete Next steps: Integration and testing the Pixel Package on surface is scheduled in next Fall DAQ integration and commissioning experience will grow in parallel Still a lot of work, but..... A 3 hit Pixel Detector is on its way to record LHC events in ATLAS

Backup

Constraints: radiation hardness External pixel layers will receive a yearly damage from NIEL corresponding to a fluence of 1014 neq/cm2 B-layer at R=5.5 cm will be a factor two more. Initial specification were: external layers must withstand 10 years of operation at the LHC B-layer must withstand at least 5 years of operation That means: NIEL >1015 neq/cm2 dose > 500 kGy Oxygenated FZ silicon was chosen because of improved hardness to charge particle irradiation.

Rad-hard Sensors Sensor modules consists of 47232 n+ pixels (mostly 50 m  400 m ) on n substrate, having an active area of 60.8 × 16.2 mm2. Pixels are insulated by a moderated p-spray implant. For sensor testing all pixel can be kept equipotential by a bias grid. In order not to loose coverage, special pixel layout (long and ganged pixels) has been chosen for the interchip regions (>200 m). Production of 2500 sensorsis finished at CiS, Germany, and on going in ON Semiconductor (TESLA), Czech Republic. before irr. : low E-field high E-field low E-field after irr. : high E-field low E-field low E-field

Angle and hit duplication Fraction of cluster with all hits in1 b. c. after duplication of hit with TOT£ 10 Efficiency plot TOT£ 5 Record! e = (100.00  0.03) % Fraction of cluster with all hits in 1 b. c.