Chapter 5 Combinational Logic 组合逻辑

Combinational Logic circuit Logic circuit Sequential Logic circuit

5.1 Basic Combinational Circuits AND-OR AND-OR-Invert XOR XNOR NAND NOR

1 AND-OR Logic X=AB+CD An AND-OR circuit directly implements SOP expression, assuming the complements of the variables are available. D A B C X & 1 A B C D X ANSI standard distinctive shape symbols ANSI standard rectangular outline symbols

Example chip: 74HC58 VCC GND 74HC58 (CMOS): dual AND-OR 2 3 4 6 & 1 9 11 8 10 12 1 13 VCC 7 14 74HC58 (CMOS): dual AND-OR 1 two inputs AND-OR. 1 three inputs AND-OR

2 AND-OR-Invert Logic An AND-OR-Invert can be used to implement POS expression. D A B C X & 1 A B C D X

Example chip: 74LS51 VCC GND 74LS51 : dual 2-wide AND-OR-Invert 3 4 6 & 1 9 11 8 10 12 1 13 VCC 7 14 74LS51 : dual 2-wide AND-OR-Invert 1 two inputs AND-OR-Invert. 1 three inputs AND-OR-Invert

3 Exclusive-OR (XOR)异或 A B C A B C

4 Exclusive-NOR (XNOR)同或 A B C A B C

5-2 IMPLEMENTING COMBINATIONAL LOGIC 实现组合逻辑

From a Boolean Expression to a Logic Circuit Example:

From a Boolean Expression to a Logic Circuit Example:

From a Truth Table to a Logic Circuit Example:

5-3 THE UNIVERSAL PROPERTY OF NAND AND NOR GATES 与非门和或非门的通用特征

The NAND Gate as a Universal Logic Element The NAND gate can be used to produce the NOT, AND, OR, and NOR operations.

The NOR Gate as a Universal Logic Element The NOR gate can be used to produce the NOT, AND, OR, and NAND operations.

5-4 COMBINATIONAL LOGIC USING NAND AND NOR GATES 使用与非门和或非门的组合逻辑

5 Combinational Logic Using NAND and NOR Gates Negative-OR Negative-AND

Example: Implementing the following expression using NAND gates: Solution: A B C D X

Example: Implementing the following expression using NOR gates: Solution: A B C D X

NAND Logic

NOR Logic

5-5 Logic Hazards Objective: Combinational logic hazards Reasons Checking Eliminating methods

Combinational Logic Hazards Static hazard Dynamic hazard

Static hazards 1 1 glitches 1 Static hazards have two cases: Static 1 : an output variable should be a 1, but goes to 0 momentarily as a result of an input variable changing. Static 0 : an output variable should be a 0, but goes to 1 momentarily as a result of an input variable changing. 1 1 glitches 1

Static 1 hazards example

glitch

Static-0 hazards example

Checking static hazards: If the circuit can be simplified as follows A+A=1 or AA=0, it has the potential to cause static hazards.

Static-0 Static-1

Exercise

exercise

5-6 OPERATION WITH PULSE WAVEFORMS 具有脉冲波形的逻辑电路运算

Logical Operation is the Same The logical operation of a gate is the same for pulse inputs as for constant-level inputs.

Homework Problems: 2 6d 9d 10c 12 22e 24g 27