Combinational Circuits and Boolean Jess Role@UEAB 2006

Common Combinational Circuits NAND gates and Duality Adders Multiplexers Jess Role@UEAB 2006

De Morgan again A NAND gate: Y = A.B = A + B is the same as an OR gate with two NOT gates Similarly a NOR gate is the same as an AND gate with two inverters Y = A + B = A.B not the individual terms change the sign not the lot Jess Role@UEAB 2006

Dual gates not the individual inputs change the gate not the output Jess Role@UEAB 2006

Truth Tables and Boolean Notation NAND Gate Representation It is possible to implement any boolean expression using only NAND gates NOT X X AND A.B A A.B B OR A A+B B Jess Role@UEAB 2006

Truth Tables and Boolean Notation NAND Gate representation Implement the following circuit using only NAND gates x2 x4 x3 De Morgan can also be represented visually: Jess Role@UEAB 2006

Solution Dual the gates, remember two nots together can be removed. x3 x2 x4 A B A.B A+B AND feeding OR Jess Role@UEAB 2006

Exercise Implement NOT, AND and OR using NOR gates Example AND gate dual circuit: Jess Role@UEAB 2006

Solution Similar pattern to using NAND gates (not surprising) NOT AND OR X A B A.B A+B Jess Role@UEAB 2006

Truth Tables and Boolean Notation NOR Gate representation It is also possible to implement any boolean expression using only NOR gates Implement the following circuit using only NOR gates X4 X3 X 2 Jess Role@UEAB 2006

Solution Two NOR gates in sequence acting as NOT’s can be eliminated: X4 X3 X 2 Jess Role@UEAB 2006

Examples The half adder A B S C 1 The half adder is a circuit for adding two single bit numbers Develop a truth table and Boolean expressions for the half adder A B S C 1 0 0 1 1 +0 +1 +0 +1 0 1 1 1 carry 1 S and C are the Sum and Carry A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 s = notA.B + BnotA = A + B c = A.B Jess Role@UEAB 2006

Half adder The sum is XOR operation and the carry an AND: A B S C 1 C 1 Jess Role@UEAB 2006

Examples The full adder Develop a truth table and Boolean expressions for the full adder, this circuit also includes a carry in. Cin A B S C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Sum A full adder B 0 0 1 1 +0 +1 +0 +1 0 1 1 1 carry 1 Cout Cin 0Cin1 0Cin1 1Cin1 1Cin1 +0 +1 +0 +1 1 0carry1 0carry1 1carry 1 SUM Cin AB 00 01 11 10 Jess Role@UEAB 2006 1 1 Cin A B S C 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 Cout A BC 00 01 11 10 1 1 1 1 1

Truth table for full adder C in A B S C out 1 Exercise: Complete the Karnaugh maps for the Sum and the Carry out columns Jess Role@UEAB 2006

K maps for sum and carry AB C in 00 01 11 10 1 AB C in 00 01 11 10 1 Sum – 1 when odd number of inputs is 1 = XOR gate Carry out - simplifies to 3 pairs AB C in 00 01 11 10 1 AB C in 00 01 11 10 1 C out = A.B + A.Cin + B.Cin Sum = Cin xor A xor B Jess Role@UEAB 2006

Full adder circuit A B Sum Count C in Sum = Cin xor A xor B Cout = A.B + A.Cin + B.Cin Jess Role@UEAB 2006

Examples The Multiplexer Selects one of 2n inputs and copies it to a single output The selected line is determined from the bit combination (address) on the n selection lines e.g. 1 from 2 mutiplexer n = 1 a out 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 sel a b out b 1 sel 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 sel a b out sel ab 00 01 11 10 A BC 00 01 11 10 1 1 1 1 1 1 out = not(sel).a + sel.b out = Jess Role@UEAB 2006

2:1 Multiplexer sel a b out ? 1 sel a b out 1 AB sel 00 01 11 10 1 ? 1 sel a b out 1 if a is selected, don’t care about b. AB sel 00 01 11 10 1 Jess Role@UEAB 2006

K map for 2:1 Multiplexer AB sel 00 01 11 10 1 output = sel.a + sel.b 1 output = sel.a + sel.b data Principal can be extended to 4:1 – 2 select lines and 4 data lines 8:1 – 3 select lines and 8 data lines and so on… out sel Jess Role@UEAB 2006

What you should be able to do: Change circuits using one set of gates (eg AND, OR, NOT) to their equivalent using NAND or NOR gates only (and vice versa). Be familiar with half-, full- adders and multiplexer circuits. Be able to construct and interpret Karnaugh maps with up to 4 input variables. Jess Role@UEAB 2006