COSC3330 Computer Architecture Lecture 2. Combinational Logic Instructor: Weidong Shi (Larry), PhD Computer Science Department University of Houston

Today Combinational Logic Boolean Algebra Mux, DeMux, Decoder

Extra Credit Question Thanks for all who submitted

Z1 Konrad Zuse: the Z1 (1938), Germany First binary programmable computer, completely mechanical Punchcard input, processing implemented with metal plates Konrad designed the first high level programming language

Zoom-in a System Component

Circuit A logic circuit is composed of Inputs Outputs Functional specification Relationship between inputs and outputs Timing specification Delay from inputs to outputs 6 6

Circuits Nodes Circuit elements Inputs: A, B, C Outputs: Y, Z Internal: n1 Circuit elements E1, E2, E3 7 7

Types of Logic Circuits Combinational Logic Outputs are determined by current values of inputs Thus, it is memoryless Sequential Logic Outputs are determined by previous and current values of inputs Thus, it has memory 8 8

Rules of Combinational Composition A circuit is combinational if Every node of the circuit is either designated as an input to the circuit or connects to exactly one output terminal of a circuit element The circuit contains no cyclic paths Every path through the circuit visits each circuit node at most once Every circuit element is itself combinational Select combinational logic? 9 9

Boolean Equations The functional specification of a combination logic is usually expressed as a truth table or a Boolean equation Truth table is in a tabular form Boolean equation is in a algebraic form Example: S = F(A, B, Cin) Cout = F(A, B, Cin) Truth Table Boolean equation 10 10

Terminology The complement of a variable A is A A variable or its complement is called literal AND of one or more literals is called a product or implicant Example: AB, ABC, B OR of one or more literals is called a sum Example: A + B Order of operations NOT has the highest precedence, followed by AND, then OR Example: Y = A + BC 11 11

Minterms A minterm is a product (AND) of literals involving all of the inputs to the function Each row in a truth table has a minterm that is true for that row (and only that row) 12 12

Sum-of-Products (SOP) Form The function is formed by ORing the minterms for which the output is true Thus, a sum (OR) of products (AND terms) All Boolean equations can be written in SOP form Y = F(A, B) = AB + AB 13 13

Boolean Algebra George Boole We learned how to write a boolean equation given a truth table But, that expression does not necessarily lead to the simplest set of logic gates One way to simplify boolean equations is to use boolean algebra Set of theorems It is like regular algebra, but in some cases simpler because variables can have only two values (1 or 0) Theorems obey the principles of duality: ANDs and ORs interchanged, 0’s and 1’s interchanged 14 14

Boolean Theorems of One Variable The prime (’) symbol denotes the dual of a statement 15 15

Boolean Theorems of One Variable T1: Identity Theorem B 1 = B B + 0 = B T2: Null Element Theorem B 0 = 0 B + 1 = 1 16 16

Boolean Theorems of One Variable Idempotency Theorem B B = B B + B = B T4: Identity Theorem B = B T5: Complement Theorem B B = 0 B + B = 1 17 17

Boolean Theorems of Several Variables 18 18

Simplifying Boolean Expressions: Example 1 Y = AB + AB = B (A + A) T8 = B (1) T5’ = B T1 19 19

Simplifying Boolean Expressions: Example 2 Y = A (AB + ABC) = A (AB (1 + C)) T8 = A (AB (1)) T2’ = A (AB) T1 = (AA)B T7 = AB T3 20 20

DeMorgan’s Theorem Powerful theorem in digital design Y = AB = A + B 1 A+ B A B A+B 1 A B 21 21

DeMorgan’s Theorem

Bubble Pushing Pushing bubbles backward (from the output) or forward (from the inputs) changes the body of the gate from AND to OR or vice versa Pushing a bubble from the output back to the inputs puts bubbles on all gate inputs Pushing bubbles on all gate inputs forward toward the output puts a bubble on the output and changes the gate body 23 23

Bubble Pushing What is the Boolean expression for this circuit? Y = AB + CD 24 24

Universal Gate A gate which can be use to create any Logic gate. Two universal gates NAND NOR

NOR as Universal Gate

From Logic to Gates Schematic A diagram of a digital circuit showing the elements and the wires that connect them together Example: Y = ABC + ABC + ABC Any Boolean equation in the SOP form can be drawn like above 27 27

Circuit Schematic Rules Inputs are on the left (or top) side of a schematic Outputs are on the right (or bottom) side of a schematic Whenever possible, gates should flow from left to right Straight wires are better to use than wires with multiple corners 28 28

Circuit Schematic Rules (cont.) Wires always connect at a T junction A dot where wires cross indicates a connection between the wires Wires crossing without a dot make no connection 29 29

Multiple Output Circuits 30 30

Don’t Cares (X) Y3 = A3 Y2 = A3 A2 Y1 = A3 A2 A1 Y0 = A3 A2 A1 A0 31

Floating: Z Output is disconnected from the input if not enabled We say output is floating, high impedance, open, or high Z Tristate Buffer An implementation Example 32 32

Where Is Tristate Buffer Used for? Tristate buffer is used when designing hardware components sharing a communication medium called “shared bus” Many hardware components can be attached on a shared bus Only one component is allowed to drive the bus at a time The other components put their outputs to the floating What happen if you don’t use the tristate buffer on shared bus? Hardware Device 0 Hardware Device 1 Hardware Device 2 shared bus Hardware Device 3 Hardware Device 4 Hardware Device 5 33 33

Timing There is always delay from input change to output change in real world One of the biggest challenges in circuit design is to make the circuit fast 34 34

Propagation & Contamination Delay Propagation delay tpd = max delay from input to output Contamination delay tcd = min delay for a change at the input to affect the output 35 35

Propagation & Contamination Delay Delay is caused by Transistor capacitance and resistance in a circuit Interconnection capacitance and resistance Reasons why tpd and tcd may be different Different rising and falling delays Multiple inputs and outputs, some of which are faster than others Circuits speeds are different depending on temperature Circuit slows down when hot Circuit speeds up when cold 36 36

Critical and Short Paths Critical (Longest) Path: tpd = 2tpd_AND + tpd_OR Short Path: tcd = tcd_AND 37 37

Digital Components Digital Components Mux Demux Decoder

Recap: Sum-of-Products (SOP) Form The function is formed by ORing the minterms for which the output is true Thus, a sum (OR) of products (AND terms) All Boolean equations can be written in SOP form Y = F(A, B) = AB + AB 39 39

Combinational Building Blocks Combinational logic is often grouped into larger building blocks to build more complex systems 2 other very commonly used digital components Multiplexers Decoders 40 40

Multiplexer (Mux) Multiplexer selects an output from inputs based on the value of a “select” signal Multiplexer is many times called a mux Example: 2:1 Mux Y = D1 S D0 + S D1 D0 Y 1 = S D1(D0+D 0) S D0 (D1+D1 )+ 1 = S D1 S D0 + S Y D0 1 D1 1 1 1 41 41

Wider Muxes 4:1 Mux 8:1 Mux 16:1 Mux N:1 Mux 4 inputs, 1 output, and 2 select signals 8:1 Mux 8 inputs, 1 output, and 3 select signals 16:1 Mux 16 inputs, 1 output, and 4 select signal N:1 Mux N inputs, 1 output, and log2N select signals 42 42

Multiplexers (Mux) Functionality: Selection of a particular input Route 1 of N inputs (A) to the output F Require selection bits (S) En(able) bit can disable the route and set F to 0 F A0 A1 A2 A3 S1 S0 En 4-to-1 Mux

Multiplexers (Mux) w/out Enable F A0 1 A1 A2 A3 A0 A1 F 4-to-1 Mux A2 A3 S1 S0

Gate Diagram S1 S0 A0 A1 A2 A3

4-to-1 Mux – Input Analysis F A0 1 A1 A2 A3 A3 S0 S1 A0 | A1 | A2 | A3 | A0 | A1 | A2 | A3 |

Multiplexers (Mux) w/ Enable F A0 A1 A2 A3 S1 S0 En 4-to-1 Mux En S1 S0 F X 1 A0 A1 A2 A3

4-to-1 Mux w/ Enable Logic S1 S0 F En A0 A1 A2 A3

4-to-1 Mux w/ Enable Logic S1 S0 En F A0 A1 Reduce one Gate Delay by using 4-input AND gate for the 2nd level A2 A3 En

A Real Multiplexer Chip 50 50

Demultiplexers (DeMux) F A0 A1 A2 A3 S1 S0 4-to-1 Mux D0 D1 1-to-4 DeMux A D2 D3 S1 S0

DeMux Operations 1-to-4 DeMux D0 D1 A D2 D3 S1 S0 S1 S0 D3 D2 D1 D0 A A 1 D0 D1 1-to-4 DeMux A D2 D3 S1 S0

DeMux Operations S1 S0 D3 D2 D1 D0 A 1 D0 D1 D2 D3 A S1 S0

DeMux – Input Analysis A S1 S0 D3 D2 D1 D0 A 1 D0 | D1 | D2| D3 | D0| A 1

DeMux Operations w/ Enable X 1 A

Decoders Decoder asserts only one of outputs depending on the input combination N inputs, 2N outputs One-hot because only one output is “hot” (HIGH) at a given time 56 56

Logic using Decoders Decoders can be combined with OR gates to build logic functions SOP form (ORing minterms) A B AB 1 AB 1 AB 1 AB 1 1 1 AB 57 57

A Real Decoder Chip 74LS138 3 inputs, 8 outputs inputs outputs 58 58