Day 3: September 10, 2012 Gates from Transistors ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 10, 2012 Gates from Transistors Penn ESE370 Fall2012 -- DeHon

Previously Simplified models for reasoning about transistor circuits Zeroth-order Penn ESE370 Fall2012 -- DeHon

Today How to construct static CMOS gates Penn ESE370 Fall2012 -- DeHon

Outline Circuit understanding Static CMOS Finish zeroth order example preclass Static CMOS Structure Inverter Construct gate Inverting Cascading Penn ESE370 Fall2012 -- DeHon

What happens when Vin=Vdd>Vth Vthp=-Vthn Vgs=-Vdd < Vthp Vgs=0 > Vthp Vout=Vdd V2=Gnd Vgs=0 < Vthn Vgs=Vdd > Vthn Penn ESE370 Fall2012 -- DeHon

What happens when Vin=0<Vth Work on board Penn ESE370 Fall2012 -- DeHon

What happens when Vin=0<Vth V2=Vdd Vout=0 Penn ESE370 Fall2012 -- DeHon

What function? Buffer Vin=Vdd  Vout=Vdd Vin=0  Vout=0 Penn ESE370 Fall2012 -- DeHon

Why Zeroth Order Useful? Allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits Make sure understand logical function (achieve logical function) before worrying about performance details Penn ESE370 Fall2012 -- DeHon

What gate? Penn ESE370 Fall2012 -- DeHon

What function? Penn ESE370 Fall2012 -- DeHon

DeMorgan’s Law /f = a + b What is f? Penn ESE370 Fall2012 -- DeHon

What function? Penn ESE370 Fall2012 -- DeHon

Static CMOS Gate Penn ESE370 Fall2012 -- DeHon

Static CMOS Gate Structure Penn ESE370 Fall2012 -- DeHon

Static CMOS Gate Structure Penn ESE370 Fall2012 -- DeHon

Static CMOS Gate Structure Drives rail-to-rail (output is Vdd or Gnd) Inputs connects to gates  load is capacitive Once charge capacitive output, doesn’t use energy (first order) Output actively driven Penn ESE370 Fall2012 -- DeHon

Inverter Out = /in Penn ESE370 Fall2012 -- DeHon

Inverter Penn ESE370 Fall2012 -- DeHon

Why zeroth-order adequate? Static analysis – can ignore capacitors Capacitive loads – resistances don’t matter Feed forward for gates – don’t generally have loops can work forward from known values Logic drive rail-to-rail Don’t have to reason about intermediate voltage levels Penn ESE370 Fall2012 -- DeHon

What zeroth-order not tell us? Delay Dynamics Behavior if not Capacitively loaded Acyclic (if there are Loops) Rail-to-rail drive Penn ESE370 Fall2012 -- DeHon

Gate Design Example Penn ESE370 Fall2012 -- DeHon

Gate Design Design gate to perform: f=(/a+/b)*/c Penn ESE370 Fall2012 -- DeHon

f=(/a+/b)*/c Strategy: Use static CMOS structure Design PMOS pullup for f Use DeMorgan’s Law to determine /f Design NMOS pulldown for /f Penn ESE370 Fall2012 -- DeHon

f=(/a+/b)*/c PMOS Pullup for f? Penn ESE370 Fall2012 -- DeHon

f=(/a+/b)*/c Use DeMorgan’s Law to determine /f. What is /f ? Penn ESE370 Fall2012 -- DeHon

f=(/a+/b)*/c NMOS Pulldown for /f? Penn ESE370 Fall2012 -- DeHon

f=(/a+/b)*/c a c b Penn ESE370 Fall2012 -- DeHon

Static CMOS Source/Drains With PMOS on top, NMOS on bottom PMOS source always at top (near Vdd) NMOS source always at bottom (near Gnd) Penn ESE370 Fall2012 -- DeHon

Inverting Gate Penn ESE370 Fall2012 -- DeHon

Inverting Stage Each stage of Static CMOS gate is inverting Penn ESE370 Fall2012 -- DeHon

How do we buffer? Penn ESE370 Fall2012 -- DeHon

How implement OR? Penn ESE370 Fall2012 -- DeHon

Cascading Stages Penn ESE370 Fall2012 -- DeHon

Stages Can always cascade “stages” to build more complex gates Could simply build nor2 at circuit level and assemble arbitrary logic by combining – universality but may not be smallest/fastest/least power Penn ESE370 Fall2012 -- DeHon

Implement: f=a*/b Pullup? Pulldown? Penn ESE370 Fall2012 -- DeHon

f=a*/b Penn ESE370 Fall2012 -- DeHon

Admin Office hours Thursday: HW1 due Friday in Detkin (RCA) Lab Today: Udit 7-8pm Ketterer Tuesday: Andre 4-5:30pm Moore/GRS 262 Wednesday: none (normally Udit 6pm Thursday: HW1 due design gates will build in lab on Friday Friday in Detkin (RCA) Lab Please read through HW2, Lab1 details Bring USB drive with you to lab on Friday to store waveforms Penn ESE370 Fall2012 -- DeHon

Big Idea Systematic construction of any gate from transistors Use static CMOS structure Design PMOS pullup for f Use DeMorgan’s Law to determine /f Design NMOS pulldown for /f Penn ESE370 Fall2012 -- DeHon