Valerio Re Università di Bergamo and INFN, Pavia, Italy FSSR2: a candidate front-end chip for striplets Valerio Re Università di Bergamo and INFN, Pavia, Italy SuperB Detector Workshop, SLAC, February 14 – 16, 2008 Making Sound Measurements and Octave Analysis

A readout chip for SuperB striplets 200-mm thick double-sided striplets (L = 1.83 cm) detectors are the baseline option for Layer0 Including a x10 safety factor, a background hit rate of 50 MHz/cm2 is expected, corresponding to a strip hit rate > 450 kHz Need for a fast, self-triggered readout architecture with no analog storage, with enough output bandwidth to ensure that no data is lost due to readout deadtime Making Sound Measurements and Octave Analysis

The FSSR2 chip Mixed-signal integrated circuit for the readout of silicon strip detectors, developed by Fermilab (R. Yarema,J.Hoff, A. Mekkaoui) and INFN-Pavia (V. Re, M. Manghisoni, L. Ratti) Final step of R&D effort begun with the design of the prototype chip FSSR TSMC 0.25 µm CMOS technology with enclosed NMOS for radiation tolerance 128 analog channels, address, time, and magnitude information for all hits Fast, self-triggered readout architecture with no analog storage, very similar to the FPIX2 chip (front-end for pixels in the BTeV experiment) Designed for the BTeV Forward Silicon Tracker, FSSR2 is suitable for a wide range of applications with microstrip detectors Making Sound Measurements and Octave Analysis

7.5 mm x 5 mm, input pads with 50 mm pitch The FSSR2 chip Front-End Core Logic Programming Interface Data output Interface 7.5 mm x 5 mm, input pads with 50 mm pitch Making Sound Measurements and Octave Analysis

FSSR2 block diagram FSSR2 Core 128 analog channels 16 sets of logic, each handling 8 channels Core logic with BCO counter (time stamp) Programming Interface (slow control) Programmable registers DACs Data Output Interface Communicates with core logic Formats data output Same as BTeV FPIX2 chip Making Sound Measurements and Octave Analysis

Analog channels (evolution of AToM chip) Preamplifier Programmable Gain To 3-bit Flash ADC Cf1 Programmable Baseline Restorer Cf Bias Hit/NoHit Discriminator + Shaper Threshold circuit Gf Comparator CD Kill BLR Single-ended/ Differential conversion - - CR-(RC)2 Vth + CAC Cinj Test Input (from Internal Pulser) Programmable Peaking time Threshold DAC (chip wide) Making Sound Measurements and Octave Analysis

Analog channels Preamplifier NMOS input device, W/L = 1500/0.45, ID = 500 mA Programmable charge sensitivity Integrator and shaper Unipolar 2nd order semigaussian shaper Four programmable shaping times (65, 85, 100, 125 nsec) Base Line Restorer Cancellation of the baseline shift due to the tail in the shaper output signal The BLR is selectable, so that it can be used only when signal occupancy is high Discriminator Binary information (hit / no hit) Programmable differential threshold (chip wide) 3 bit Flash ADC Pulse amplitude information for detector monitoring and calibration Making Sound Measurements and Octave Analysis

Digital section Programming Interface Data Output Interface Accepts commands and data from serial input bus Programmable registers hold input values for DACs providing reference currents and voltages to the core (discriminator thresholds, test signal amplitude,…) Data Output Interface Serializes data from the core and transmits data off chip Programmable number of output LVDS lines (1, 2, 4, 6) Maximum data transmission rate 840 Mb/s Output data word includes 3 bits for ADC pulse amplitude information, 5 bits for the logic set number, 4 bits for strip number and 8 bits for hit BCO number (time stamp) Making Sound Measurements and Octave Analysis

Test results The chip is fully functional and meets all specifications Power dissipation is 4 mW/channel The chip has been operated with a 70 MHz readout clock to provide 840 Mb output data rate. Operation at 132 ns (2% strip occupancy) or 396 ns (6 % strip occupancy) beam crossing is possible with 99% efficiency Threshold dispersion = 300 e rms (with BLR, high gain setting) ENC = 800 e rms (CD = 20 pF, peaking time = 85 nsec, with BLR) Making Sound Measurements and Octave Analysis

Charge sensitivity at shaper output: Shaper output response Charge sensitivity at shaper output: Low gain: 120 mV/fC High gain: 160 mV/fC Making Sound Measurements and Octave Analysis

Baseline restorer Shaper output has small overshoot. Overshoot causes unwanted variable offset at discriminator input. BLR removes variable offset. Input signal discriminator scan without BLR Input signal discriminator scan with BLR Making Sound Measurements and Octave Analysis

Equivalent Noise Charge Striplets capacitance + strays The BLR improves the threshold dispersion (AC coupling), but increases noise However, ENC is below 1000 e rms at CD = 20 pF. Making Sound Measurements and Octave Analysis

However, ENC is well below the spec value of 1000 e rms at CD = 20 pF. Equivalent Noise Charge The BLR improves the threshold dispersion (AC coupling), but increases noise However, ENC is well below the spec value of 1000 e rms at CD = 20 pF. Making Sound Measurements and Octave Analysis

Radiation tolerance 200 krad/yr (including safety factor ) are expected at the striplets readout chip location FSSR prototype Irradiation with 27 MeV protons to a 1.9x1013 cm-2 fluence, corresponding to a total ionizing dose of 5 MRad After irradiation the chip remains fully functional with very little (< 10 %) degradation of critical parameters such as ENC and threshold dispersion FSSR2 Irradiation with 60Co g-rays to a total ionizing dose of 20 Mrad (no bias applied during irradiation) Chip fully functional after irradiation; noise and charge sensitivity are not affected Threshold dispersion with BLR selected increases by about 15 % (remains below the spec value of 500 e rms) Making Sound Measurements and Octave Analysis

FSSR2 for L0 striplets In SuperB L0 expected FSSR2 chip occupancy (132 ns) = 6% Should be OK for pattern recognition Is FSSR2 fast enough for SuperB? YES, if you believe to simulation performed for BTeV FSSR2 chip optimized for BTeV operation: With 2 interactions/bunch crossing (132 ns), expected BTeV FSSR2 occupancy 2% With standard operation (132 ns BCO clock) FSSR2 can handle 2% occupancy with efficiency > 99%. FSSR2 Simulation performed for BTeV with 6% occupancy (6 interactions/bunch crossing) indicates: Efficiency ~ 96.5%, with standard BCO clock frequency Can improve efficiency (~ 98.5%) with x 4 BCO clock frequency. FSSR2 chip can read L0 striplets (6% occupancy) with 98.5% efficiency G.Rizzo SuperB Det. Meeting 12/12/2006 Making Sound Measurements and Octave Analysis

FSSR Efficiency Verilog Simulation (Jim Hoff - Fermilab) Green and light blue lines corresponds to performance with 65 ns peaking time Improve efficiency with x 4 BCO clock frequency (30 MHz) I = Occupancy (%) G.Rizzo SuperB Det. Meeting 12/12/2006 Making Sound Measurements and Octave Analysis

FSSR2 for SuperB: what is needed? The 128-channel chip FSSR2 is fully functional and meets demanding specifications in terms of noise and threshold dispersion FSSR2 will be used for the readout of strip detectors in a beam test of a tracking system demonstrator which will also include a MAPS-based pixel prototype Tuning FSSR2 to SuperB Layer0: - add a polarity selection feature for optimal performance on both detector sides - revise efficiency performance with SuperB physics simulation data - upgrade of high data rate handling may require a redesign of the analog section (faster signal shaping) as well as of digital blocks - …… An upgraded version of FSSR2 might have to be redesigned in a 130nm CMOS technology. Making Sound Measurements and Octave Analysis

Backup slides Making Sound Measurements and Octave Analysis

Threshold circuit input Baseline restorer _ + Shaper output COMPVREF I 2I Threshold circuit input Making Sound Measurements and Octave Analysis

Baseline restorer Making Sound Measurements and Octave Analysis

Threshold dispersion [e rms]   Peaking time [ns] Threshold dispersion [e rms] Low Gain High Gain Channels with BLR deselected 65 580 460 85 600 470 125 615 485 Channels with BLR selected 440 295 290 490 280 Making Sound Measurements and Octave Analysis

Output data format Making Sound Measurements and Octave Analysis

Making Sound Measurements and Octave Analysis