AIDA design review 31 July 2008 Davide Braga Steve Thomas ASIC Design Group 31 July 2008

Overview x10 stage amplifier Peak Hold circuit Power supply stabilization Bias circuit – 8 bit DACs Offset (statistical analysis) and comparator threshold

Single channel simulation

Peak Hold nMOS & pMOS Peak Hold in parallel, for both signal polarities use of 5V transistors with low leakage to allow read out in ~ms time scale (~0.25V/s droop) pMOS PH Shaper_out Hold Reset Enable_pPH nMOS PH Hold Reset Enable_nPH

Peak Hold: linearity pMOS PH nMOS PH Good integral non-linearity over wide voltage range for both architectures

Peak Hold: minimum detectable signal Minimum detectable signal affected by input offset pMOS PH: ~10mV nMOS PH: ~4mV Input offset

Low Energy Channel

Bias circuit: current Biasing optimized to limit the current variation, but when preAmp output below ~200mV big change in current. For better power supply stabilization may be appropriate to limit ref_low to 200mV (→1.4V output swing)

Bias circuit Several internal reference voltages need to be selectable in order to adjust the operating point of the circuit for the best performance preAmp input reference Shaper/PeakHold reference Shaper bias preAmp bias

Bias circuit: 8bit DAC nMOS (up to Vdd) and pMOS (down to gnd) DAC for voltage setting Also comparator threshold must be selectable

Offset (Monte Carlo results) Offset preamp: σ~0.5mV (AC coupled to shaper, does not propagate to comparator) Offset shaper: σ~2mV Offset x10 stage: σ~3mV Offset comparator: σ~30mV! (~ 10 times offset previous stage!)

Offset Shaper input offset x10 stage in.offset Comparator in.offset

Offset reduction example of offset reduction technique Some kind of offset cancellation technique must be implemented to achieve required comparator sensitivity comparator threshold: 0.25%-10% FSR → after x10 stage 2.5%-100% FSR≈1.5V → ≈37.5mV

Conclusion complete channel analog/digital simulation to be completed soon next submission dates: end of September, end of October limitations to low threshold operation identified, to be improved in a second iteration to avoid further delay September timescale still feasible if layout straightforward