Introduction To VHDL 2002. 12. 27 홍 원 의

Contents General Basic Rule Combinational Logic Process Sequential Statements Simulation Variables, Signals, and Constants Data Type Arrays Operators Functions Procedures Packages and Libraries

General Digital system become more complex Competing to build cost-effective products as fast as possible Detailed design at gate & flip-flop level : tedious, time consuming → Using top-down design methodology (HDL, synthesis, …) → VHDL : logic & transistor level design → abstract programming Advantages shorter development cycles with more product feature and reduce time to market design reuse is enabled increased flexibility to design changes better and easier design auditing and verification

Basic Rule not case sensitive identifier rule : letters, numbers, underscore character (no space, start with a letter, not end with an underscore) command must end with semi-colon comment : -- Entity declaration : input, output Architecture body : internal behavior VHDL Program Structure Entity Architecture Entity Architecture Module 1 Entity Architecture Module 2 Entity Architecture Module N

Basic Rule entity entity-name is [ port (interface-signal-declaration); ] end [entity] [entity-name]; architecture architecture-name of entity-name is [declarations] begin architecture body end [architecture] [architecture-name]; Interface signal form: list-of-interface-signal : mode type [ := initial-value ] {; list-of-interface-signal : mode type [ := initial-value ] }

Combinational Logic A C C <= A and B after 5 ns; B E <= C or D after 5 ns; B E D VHDL signal assignments are concurrent statements when they are not in a process or block. The VHDL simulator monitors the right-hand side of each concurrent statement, and any time a signal changes, the expression on the right -hand side is immediately re-evaluated. The order of the preceding statements is unimportant. CLK <= not CLK after 10 ns; ( implicit loop )

Process a common way of modeling sequential logic in VHDL external : paralleled, internal : sequentially [label:] process [(sensitivity-list)] begin sequential-statements end process [label] ; difference in the way sequential and concurrent statements are executed concurrent Sequential (B,C,D) A <= B; B <= C; C <= D; Time delta A B C D 0 +0 1 2 3 0 10 +0 1 2 3 4 10 +1 1 2 4 4 10 +2 1 4 4 4 10 +3 4 4 4 4 Time delta A B C D 0 +0 1 2 3 0 10 +0 1 2 3 4 10 +1 2 3 4 4 10 +2 3 4 4 4 10 +3 4 4 4 4 A,B,C,D : signal A=1, B=2, C=3, D=0 D=1 @ T=10

Sequential Statements variable assignment case statement case expression is when choice1 => sequential statement1 when choice2 => sequential statement2 … [when others => sequential statements] end case; cf. conditional signal assignment (in concurrent statement) signal-name <= expression1 when condition1 else expression2 when condition2 … [else expressionN];

Sequential Statements if statement if condition then sequential statements {elsif condition then sequential statements} [else sequential statements] end if; wait statement wait on sensitivity-list : wait until sensitivity-list changes wait for time-expression wait until boolean-expression for loop [loop-label] for loop-index in range loop sequential statements end loop [loop-label]; exit; or exit when condition;

Simulation Example After elaboration: entity simulation_example is '0' A entity simulation_example is end simulation_example; architecture test1 of simulation_example is signal A, B : bit; begin P1: process(B) A <= '1'; A <= transport '0' after 5 ns; end process P1; P2: process(A) if A = '1' then B <= not B after 10 ns; end if; end process P2; end test1; time = 0 B After initialization: '0' @ 5 '1' @ ∆ '0' A time = 0 B Simulation step: '0' @ 5 '1' '1' @ 10 '0' A time = ∆ B '0' '1' @ 10 A time = 5 B '0' @ 15 '1'@ 10+∆ '0' '1' A time = 10 B '0' @ 15 '1' '0' @ 20 time = 10 + ∆ A B '0' '0' @ 20 '1' time = 15 A B

Variables, Signals, and Constants Signal : wiring, connecting component declared at the start of architecture can be used anywhere within architecture assignment ("S <= S0 after delay") Variable : temporary storage, has locality declared within process function, procedure assignment ("V := V0", immediately) Constant : declared at the start of architecture → anywhere within the architecture declared within a process → local to that process signal list_of_signal_names : type_name [ := initial_value ]; port (list_of_signal_names : mode type [ := initial_value ];) variable list_of_variable_names : type_name [ :=initial_value]; constant constant_name : type_name := constant_value;

Data Type Scalar Type Enumeration Type : bit, boolean, character Integer Type : integer ( -(231-1) ~ +(231-1) ) Float Type : real ( -1.0E38 ~ +1.0E38 ) Physical Type : time Composite Type Array Type : to, downto, bit_vector, string Record Type: record Access Type Access Type : access, new File Type File Type : file Subtype : allows the values to be constrained subset of some base type subtype identifier is subtype_indication; subtype natural is integer range 0 to highest_integer

Arrays type array_type_name is array index_range of element_type; signal array_name : array_type_name [ := initial_value ]; One-dimensional array type SHORT_WORD is array (15 downto 0) of bit; signal DATA_WORD : SHORT_WORD; Multi-dimensional array type matrix4x3 is array (1 to 4, 1 to 3) of integer; variable matrixA : matrix4x3 := ((1,2,3), (4,5,6), (7,8,9), (10,11,12)); Unconstrained type invec is array (natural range <>) of integer; signal invec5 : invec (1 to 5) := (3, 2, 6, 8, 1); Subtype type bit_vector is array (natural range <>) of bit subtype SHORT_WORD is bit_vector (15 downto 0);

Operators can be grouped into seven classes : Binary Logical Operators : and or nand nor xor xnor Ralational Operators : = /= < <= > >= Shift Operators : sll srl sla sra sra rol ror Adding Operators : + - &(concatenation) Unary Sign Operators : + - Multiplying Operators : * / mod rem Miscellaneous Operators : not abs ** Operators in class 7 have the highest precedence follow by class 6, then class 5, … Operators in the same class are applied from left to right in an expression. The precedence order can be changed by using parentheses.

Functions execute sequential algorithm and return a single value to calling program Function declaration : function function-name(formal-parameter-list) return return-type is [declarations] begin sequential statements -- must include return return_value end function-name Function call : function-name(actual-parameter-list)

Procedures facilitate decomposition of VHDL code into modules return any number of values using output parameters procedure declaration : procedure procedure_name(formal-parameter-list) is [declaration] begin sequential statements end procedure-name; procedure call : procedure_name(actual-parameter-list); formal-parameter-list [class] list-of-parameter : mode type; ※ If the class is omitted, constant is used as default. For a constant parameter, the actual parameter can be any expression.

Packages and Libraries provides a convenient way of referencing frequently used functions and components package declaration package package-name is package declarations end [package] [package-name]; type, signal, function, procedure, component declaration optional package body package body package-name is package body declaration end [package body] [package-name]; function, procedure body, entity-architecture library BITLIB; → allows to access the BITLIB; use BITLIB.bit_pack.all; → allows to use bit_pack package use BITLIB.bit_pack.Nand2; → allows to use a specific component or function in the package